| 8006153 |
Multiple uses for BIST test latches |
Steven R. Ferguson, Osamu Takahashi, Michael Brian White |
2011-08-23 |
| 7574642 |
Multiple uses for BIST test latches |
Steven R. Ferguson, Osamu Takahashi, Michael Brian White |
2009-08-11 |
| 7562267 |
Methods and apparatus for testing a memory |
Anthony Gus Aipperspach, Louis Bernard Bushard, Akihiko Fukui |
2009-07-14 |
| 7117400 |
Memory device with data line steering and bitline redundancy |
Kevin A. Batson, Robert E. Busch, Fred J. Towler, Reid A. Wistort |
2006-10-03 |
| 7003704 |
Two-dimensional redundancy calculation |
R. Dean Adams, Thomas J. Eckenrode, Steven Lee Gregor |
2006-02-21 |
| 6430073 |
Dram CAM cell with hidden refresh |
Kevin A. Batson, Robert E. Busch |
2002-08-06 |
| 6282144 |
Multi-ported memory with asynchronous and synchronous protocol |
Kevin A. Batson, Sebastian T. Ventrone |
2001-08-28 |
| 6026505 |
Method and apparatus for real time two dimensional redundancy allocation |
Erik L. Hedberg |
2000-02-15 |
| 5918003 |
Enhanced built-in self-test circuit and method |
Michael R. Ouellette, Reid A. Wistort |
1999-06-29 |
| 5859804 |
Method and apparatus for real time two dimensional redundancy allocation |
Erik L. Hedberg |
1999-01-12 |
| 5796745 |
Memory array built-in self test circuit for testing multi-port memory arrays |
Robert Dean Adams, John Connor, Luigi Ternullo, Jr. |
1998-08-18 |
| 5790564 |
Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor |
Robert Dean Adams, John Connor, Luigi Ternullo, Jr. |
1998-08-04 |
| 5784323 |
Test converage of embedded memories on semiconductor substrates |
Robert Dean Adams, John Connor, Luigi Ternullo, Jr. |
1998-07-21 |
| 5771242 |
Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor |
Robert Dean Adams, John Connor, Luigi Ternullo, Jr. |
1998-06-23 |
| 5761213 |
Method and apparatus to determine erroneous value in memory cells using data compression |
Robert Dean Adams, John Connor, Luigi Ternullo, Jr. |
1998-06-02 |
| 5745498 |
Rapid compare of two binary numbers |
Robert Dean Adams, John Connor, Luigi Ternullo, Jr. |
1998-04-28 |
| 5740098 |
Using one memory to supply addresses to an associated memory during testing |
Robert Dean Adams, John Connor, James J. Covino, Roy C. Flaker, Alan L. Roberts +2 more |
1998-04-14 |
| 5563833 |
Using one memory to supply addresses to an associated memory during testing |
Robert Dean Adams, John Connor, James J. Covino, Roy C. Flaker, Alan L. Roberts +2 more |
1996-10-08 |
| 5535164 |
BIST tester for multiple memories |
Robert Dean Adams, John Connor, Stuart Rapoport, Luigi Ternullo, Jr. |
1996-07-09 |
| 5317573 |
Apparatus and method for real time data error capture and compression redundancy analysis |
Orest Bula, Justin A. Woyke, Richard S. Gomez |
1994-05-31 |
| 5093584 |
Self calibrating timing circuit |
Justin A. Woyke, Orest Bula, Richard S. Gomez |
1992-03-03 |
