Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7102421 | Dynamically adjustable on-chip supply voltage generation | Michael C. Stephens, Jr. | 2006-09-05 |
| 6353903 | Method and apparatus for testing differential signals | Robert Dean Adams, John Connor, Donald Albert Evans | 2002-03-05 |
| 6327215 | Local bit switch decode circuit and method | Howard C. Kirsch | 2001-12-04 |
| 6246619 | Self-refresh test time reduction scheme | Christopher Ematrudo, Jeffrey Earl, Michael C. Stephens, Jr., Michael F. Vincent | 2001-06-12 |
| 6208197 | Internal charge pump voltage limit control | Michael C. Stephens, Jr. | 2001-03-27 |
| 6133748 | Crow-bar current reduction circuit | — | 2000-10-17 |
| 6111447 | Timing circuit that selectively triggers on a rising or falling input signal edge | — | 2000-08-29 |
| 6061296 | Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices | Christopher Ematrudo, Michael C. Stephens, Jr. | 2000-05-09 |
| 6060873 | On-chip-generated supply voltage regulator with power-up mode | Michael C. Stephens, Jr., Jeffrey Earl | 2000-05-09 |
| 6052328 | High-speed synchronous write control scheme | Michael C. Stephens, Jr. | 2000-04-18 |
| 6016072 | Regulator system for an on-chip supply voltage generator | Michael C. Stephens, Jr. | 2000-01-18 |
| 5996097 | Testing logic associated with numerous memory cells in the word or bit dimension in parallel | Donald Albert Evans | 1999-11-30 |
| 5973895 | Method and circuit for disabling a two-phase charge pump | Jeffrey Earl | 1999-10-26 |
| 5954830 | Method and apparatus for achieving higher performance data compression in ABIST testing by reducing the number of data outputs | — | 1999-09-21 |
| 5796745 | Memory array built-in self test circuit for testing multi-port memory arrays | Robert Dean Adams, John Connor, Garrett Stephen Koch | 1998-08-18 |
| 5796665 | Semiconductor memory device with improved read signal generation of data lines and assisted precharge to mid-level | Michael C. Stephens, Jr. | 1998-08-18 |
| 5790564 | Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor | Robert Dean Adams, John Connor, Garrett Stephen Koch | 1998-08-04 |
| 5784323 | Test converage of embedded memories on semiconductor substrates | Robert Dean Adams, John Connor, Garrett Stephen Koch | 1998-07-21 |
| 5771242 | Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor | Robert Dean Adams, John Connor, Garrett Stephen Koch | 1998-06-23 |
| 5761213 | Method and apparatus to determine erroneous value in memory cells using data compression | Robert Dean Adams, John Connor, Garrett Stephen Koch | 1998-06-02 |
| 5757050 | Field effect transistor having contact layer of transistor gate electrode material | Eric Adler, Subhash B. Kulkarni, Randy W. Mann, Werner Rausch | 1998-05-26 |
| 5744384 | Semiconductor structures which incorporate thin film transistors | Eric Adler, Subhash B. Kulkarni, Randy W. Mann, Werner Rausch | 1998-04-28 |
| 5745498 | Rapid compare of two binary numbers | Robert Dean Adams, John Connor, Garrett Stephen Koch | 1998-04-28 |
| 5740098 | Using one memory to supply addresses to an associated memory during testing | Robert Dean Adams, John Connor, James J. Covino, Roy C. Flaker, Garrett Stephen Koch +2 more | 1998-04-14 |
| 5670812 | Field effect transistor having contact layer of transistor gate electrode material | Eric Adler, Subhash B. Kulkarni, Randy W. Mann, Werner Rausch | 1997-09-23 |