MJ

Michael C. Stephens, Jr.

I1 Iii Holdings 12: 16 patents #5 of 264Top 2%
AT AT&T: 12 patents #1,455 of 18,772Top 8%
VS Vanguard International Semiconductor: 11 patents #52 of 585Top 9%
TI Texas Instruments: 6 patents #2,401 of 12,488Top 20%
AS Alliance Semiconductor: 5 patents #8 of 32Top 25%
Cypress Semiconductor: 3 patents #568 of 1,852Top 35%
📍 Los Gatos, CA: #85 of 2,986 inventorsTop 3%
🗺 California: #4,640 of 386,348 inventorsTop 2%
Overall (All Time): #30,931 of 4,157,543Top 1%
68
Patents All Time

Issued Patents All Time

Showing 1–25 of 68 patents

Patent #TitleCo-InventorsDate
11935578 Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements 2024-03-19
11632291 System facilitating prediction, detection and mitigation of network or device issues in communication systems Arthur Richard Brisebois 2023-04-18
11398267 Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements 2022-07-26
11197167 Facilitation of self-adjusting network uplink noise balancing Arthur Richard Brisebois 2021-12-07
10958508 System facilitating prediction, detection and mitigation of network or device issues in communication systems Arthur Richard Brisebois 2021-03-23
10923176 Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements 2021-02-16
10743187 Facilitation of self-adjusting network uplink noise balancing Arthur Richard Brisebois 2020-08-11
10497425 Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements 2019-12-03
10419274 System facilitating prediction, detection and mitigation of network or device issues in communication systems Arthur Richard Brisebois 2019-09-17
10199087 Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements 2019-02-05
9986439 Facilitation of self-adjusting network uplink noise balancing Arthur Richard Brisebois 2018-05-29
9906218 Dual-gate transistor control based on calibration circuitry 2018-02-27
9806708 Reference level adjustment for calibration of dual-gate transistors 2017-10-31
9659628 Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements 2017-05-23
9601167 Semiconductor device having dual-gate transistors and calibration circuitry 2017-03-21
9510176 Portable device emergency beacon 2016-11-29
9455001 Semiconductor memory device having calibration circuitry for dual-gate transistors associated with a memory array 2016-09-27
9445376 Facilitation of self-adjusting network uplink noise balancing Arthur Richard Brisebois 2016-09-13
9424888 Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements 2016-08-23
9344080 Dual-gate transistor control based on calibration circuitry 2016-05-17
9304525 Reference level adjustment for calibration of dual-gate transistors 2016-04-05
9286955 Semiconductor memory device having calibration circuitry for dual-gate transistors associated with a memory array 2016-03-15
9218854 Stack position determination in memory devices configured for stacked arrangements 2015-12-22
9189951 Portable device emergency beacon 2015-11-17
9183891 Memory devices with serially connected signals for stacked arrangements 2015-11-10