Issued Patents All Time
Showing 51–68 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6060873 | On-chip-generated supply voltage regulator with power-up mode | Luigi Ternullo, Jr., Jeffrey Earl | 2000-05-09 |
| 6061296 | Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices | Luigi Ternullo, Jr., Christopher Ematrudo | 2000-05-09 |
| 6052328 | High-speed synchronous write control scheme | Luigi Ternullo, Jr. | 2000-04-18 |
| 6018489 | Mock wordline scheme for timing control | — | 2000-01-25 |
| 6016072 | Regulator system for an on-chip supply voltage generator | Luigi Ternullo, Jr. | 2000-01-18 |
| 5999477 | Distributed array activation arrangement | — | 1999-12-07 |
| 5796665 | Semiconductor memory device with improved read signal generation of data lines and assisted precharge to mid-level | Luigi Ternullo, Jr. | 1998-08-18 |
| 5565764 | Digital processing method for parameter estimation of synchronous, asynchronous, coherent or non-coherent signals | Leslie A. Priebe, William D. Daniels | 1996-10-15 |
| 5559752 | Timing control circuit for synchronous static random access memory | Chitranjan N. Reddy, Kenneth A. Poteet | 1996-09-24 |
| 5550783 | Phase shift correction circuit for monolithic random access memory | Ajit K. Medhekar | 1996-08-27 |
| 5550500 | Timing delay modulation scheme for integrated circuits | Ajit K. Medhekar | 1996-08-27 |
| 5548560 | Synchronous static random access memory having asynchronous test mode | Ajit K. Medhekar, Chitranjan N. Reddy | 1996-08-20 |
| 5517137 | Synchronous self-timed clock pulse circuit having improved power-up performance | — | 1996-05-14 |
| 5469385 | Output buffer with boost from voltage supplies | Scott E. Smith, Duy-Loan T. Le, Masayoshi Nomura | 1995-11-21 |
| 5450364 | Method and apparatus for production testing of self-refresh operations and a particular application to synchronous memory devices | Vipul Patel | 1995-09-12 |
| 5386385 | Method and apparatus for preventing invalid operating modes and an application to synchronous memory devices | — | 1995-01-31 |
| 5347184 | Dual receiver edge-triggered digital signal level detection system | Roger D. Norwood, Duy-Loan T. Le, Kenneth A. Poteet | 1994-09-13 |
| 5295101 | Array block level redundancy with steering logic | Scott E. Smith, Charles J. Pilch, Jr., Duy-Loan T. Le, Terry T. Tsai, Arthur R. Piejko | 1994-03-15 |