KP

Kenneth A. Poteet

TI Texas Instruments: 14 patents #973 of 12,488Top 8%
AS Alliance Semiconductor: 7 patents #6 of 32Top 20%
Overall (All Time): #212,033 of 4,157,543Top 6%
21
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
6088280 High-speed memory arranged for operating synchronously with a microprocessor Wilbur C. Vogley, Anthony M. Balistreri, Karl M. Guttag, Steven D. Krueger, Duy-Loan T. Le +3 more 2000-07-11
5982694 High speed memory arranged for operating synchronously with a microprocessor Wilbur C. Vogley, Anthony M. Balistreri, Karl M. Guttag, Steven D. Krueger, Duy-Loan T. Le +3 more 1999-11-09
5912854 Data processing system arranged for operating synchronously with a high speed memory Wilbur C. Vogley, Anthony M. Balistreri, Karl M. Guttag, Steven D. Krueger, Duy-Loan T. Le +3 more 1999-06-15
5872742 Staggered pipeline access scheme for synchronous random access memory Subramani Kengeri, Darryl G. Walker, Chitranjan N. Reddy 1999-02-16
5808959 Staggered pipeline access scheme for synchronous random access memory Subramani Kengeri, Darryl G. Walker, Chitranjan N. Reddy 1998-09-15
5808958 Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock Wilbur C. Vogley, Anthony M. Balistreri, Karl M. Guttag, Steven D. Krueger, Duy-Loan T. Le +3 more 1998-09-15
5678021 Apparatus and method for a memory unit with a processor integrated therein Basavaraj I. Pawate, Joe H. Neal 1997-10-14
5633832 Reduced area word line driving circuit for random access memory Vipul Patel, Chitranjan N. Reddy 1997-05-27
5617555 Burst random access memory employing sequenced banks of local tri-state drivers Vipul Patel, Chitranjan N. Reddy 1997-04-01
5587954 Random access memory arranged for operating synchronously with a microprocessor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock Wilbur C. Vogley, Anthony M. Balistreri, Karl M. Guttag, Steven D. Krueger, Duy-Loan T. Le +3 more 1996-12-24
5559752 Timing control circuit for synchronous static random access memory Michael C. Stephens, Jr., Chitranjan N. Reddy 1996-09-24
5535172 Dual-port random access memory having reduced architecture Chitranjan N. Reddy 1996-07-09
5532966 Random access memory redundancy circuit employing fusible links Chitranjan N. Reddy 1996-07-02
5410510 Process of making and a DRAM standby charge pump with oscillator having fuse selectable frequencies Scott E. Smith, Duy-Loan T. Le, Michael V. Ho 1995-04-25
5402390 Fuse selectable timing signals for internal signal generators Duc Ho, Duy-Loan T. Le, Scott E. Smith 1995-03-28
5390149 System including a data processor, a synchronous dram, a peripheral device, and a system clock Wilbur C. Vogley, Anthony M. Balistreri, Karl M. Guttag, Steven D. Krueger, Duy-Loan T. Le +3 more 1995-02-14
5347184 Dual receiver edge-triggered digital signal level detection system Michael C. Stephens, Jr., Roger D. Norwood, Duy-Loan T. Le 1994-09-13
5287311 Method and apparatus for implementing .times.2 parity DRAM for 16 bit systems from .times.4 parity DRAM Jim C. Tso, Vipul Patel 1994-02-15
5228132 Memory module arranged for data and parity bits Joseph H. Neal 1993-07-13
5089993 Memory module arranged for data and parity bits Joseph H. Neal 1992-02-18
5075572 Detector and integrated circuit device including charge pump circuits for high load conditions Duy-Loan T. Le 1991-12-24