Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9802161 | Fluid treatment assemblies | Cheryl Ann SAYER, Sylvia Messier | 2017-10-31 |
| 6854041 | DRAM-based separate I/O memory solution for communication applications | Kevin G. Petrunich, Harold Pilo | 2005-02-08 |
| 6737894 | Method and apparatus for generating impedance matched output signals for an integrated circuit device | — | 2004-05-18 |
| 6134182 | Cycle independent data to echo clock tracking circuit | Harold Pilo | 2000-10-17 |
| 6038181 | Efficient semiconductor burn-in circuit and method of operation | George M. Braceras, Richard E. Hee, Harold Pilo | 2000-03-14 |
| 5841720 | Folded dummy world line | Alan L. Roberts, Jose R. Sousa | 1998-11-24 |
| 5740098 | Using one memory to supply addresses to an associated memory during testing | Robert Dean Adams, John Connor, Roy C. Flaker, Garrett Stephen Koch, Alan L. Roberts +2 more | 1998-04-14 |
| 5721863 | Method and structure for accessing semi-associative cache memory using multiple memories to store different components of the address | Roy C. Flaker, Alan L. Roberts, Jose R. Sousa | 1998-02-24 |
| 5715188 | Method and apparatus for parallel addressing of CAMs and RAMs | Roy C. Flaker, Alan L. Roberts, Jose R. Sousa | 1998-02-03 |
| 5650733 | Dynamic CMOS circuits with noise immunity | — | 1997-07-22 |
| 5631868 | Method and apparatus for testing redundant word and bit lines in a memory array | Luigi Termullo, Jr., Marcel J. Robillard, Stuart J. Hall | 1997-05-20 |
| 5625302 | Address buffer for synchronous system | Jose R. Sousa | 1997-04-29 |
| 5563833 | Using one memory to supply addresses to an associated memory during testing | Robert Dean Adams, John Connor, Roy C. Flaker, Garrett Stephen Koch, Alan L. Roberts +2 more | 1996-10-08 |
| 5559453 | Interlocked restore circuit | Jose R. Sousa | 1996-09-24 |