Issued Patents All Time
Showing 25 most recent of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11593117 | Combining load or store instructions | Harsh Thakker, Thomas Philip Speier, Rodney Wayne Smith, Kevin JAGET, James Norris Dieffenderfer +5 more | 2023-02-28 |
| 11550723 | Method, apparatus, and system for memory bandwidth aware data prefetching | Niket K. Choudhary, David Scott Ray, Thomas Philip Speier, Eric F. Robinson, Harold W. Cain, III +3 more | 2023-01-10 |
| 11061822 | Method, apparatus, and system for reducing pipeline stalls due to address translation misses | Pritha Ghoshal, Niket K. Choudhary, Ravi Rajagopalan, Patrick Eibl, David Scott Ray +1 more | 2021-07-13 |
| 10956162 | Operand-based reach explicit dataflow processors, and related methods and computer-readable media | Robert Douglas Clancy, Melinda J. Brown, Yusuf Cagatay Tekmen, Michael Scott McIlvaine, Thomas Philip Speier +3 more | 2021-03-23 |
| 10877895 | Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions | Luke Yen, Niket K. Choudhary, Pritha Ghoshal, Thomas Philip Speier, William James McAvoy +1 more | 2020-12-29 |
| 10318436 | Precise invalidation of virtually tagged caches | William James McAvoy, Spencer E. Williams, Robert Douglas Clancy, Michael Scott McIlvaine, Thomas Philip Speier | 2019-06-11 |
| 10108419 | Dependency-prediction of instructions | James Norris Dieffenderfer, Michael Scott McIlvaine, Melinda J. Brown | 2018-10-23 |
| 9858077 | Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable media | Melinda J. Brown, James Norris Dieffenderfer, Michael William Morrow, Michael Scott McIlvaine | 2018-01-02 |
| 9823929 | Optimizing performance for context-dependent instructions | Daren Eugene Streett, Thomas Philip Speier, Rodney Wayne Smith, Michael Scott McIlvaine, Kenneth Alan Dockser +1 more | 2017-11-21 |
| 9477478 | Multi level indirect predictor using confidence counter and program counter address filter scheme | Kulin N. Kothari, Michael William Morrow, James Norris Dieffenderfer, Michael Scott McIlvaine, Daren Eugene Streett | 2016-10-25 |
| 9477476 | Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media | Melinda J. Brown, Michael William Morrow, James Norris Dieffenderfer, Michael Scott McIlvaine, Rodney Wayne Smith +2 more | 2016-10-25 |
| 9460018 | Method and apparatus for tracking extra data permissions in an instruction cache | Leslie Mark DeBruyne, James Norris Dieffenderfer, Michael Scott McIlvaine | 2016-10-04 |
| 9411590 | Method to improve speed of executing return branch instructions in a processor | Rodney Wayne Smith, Jeffery M. Schottmiller, Michael Scott McIlvaine, Melinda J. Brown, Daren Eugene Streett | 2016-08-09 |
| 9329930 | Cache memory error detection circuits for detecting bit flips in valid indicators in cache memory following invalidate operations, and related methods and processor-based systems | John Ingalls, Thomas Philip Speier | 2016-05-03 |
| 9317293 | Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media | James Norris Dieffenderfer, Michael William Morrow, Michael Scott McIlvaine, Daren Eugene Streett, Vimal Reddy | 2016-04-19 |
| 9195466 | Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable media | Melinda J. Brown, James Norris Dieffenderfer, Michael Scott McIlvaine, Rodney Wayne Smith, Jeffery M. Schottmiller +2 more | 2015-11-24 |
| 9146741 | Eliminating redundant masking operations instruction processing circuits, and related processor systems, methods, and computer-readable media | Melinda J. Brown, Michael William Morrow, James Norris Dieffenderfer, Michael Scott McIlvaine | 2015-09-29 |
| 8943300 | Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information | James Norris Dieffenderfer, Thomas Andrew Sartorius, Rodney Wayne Smith | 2015-01-27 |
| 8898437 | Predecode repair cache for instructions that cross an instruction cache line | Rodney Wayne Smith, David John Mandzak, James Norris Dieffenderfer | 2014-11-25 |
| 8819342 | Methods and apparatus for managing page crossing instructions with different cacheability | Leslie Mark DeBruyne, James Norris Dieffenderfer, Michael Scott McIlvaine | 2014-08-26 |
| 8438371 | Link stack repair of erroneous speculative update | James Norris Dieffenderfer, Rodney Wayne Smith | 2013-05-07 |
| 8438372 | Link stack repair of erroneous speculative update | James Norris Dieffenderfer, Rodney Wayne Smith | 2013-05-07 |
| 8352713 | Debug circuit comparing processor instruction set operating mode | Kevin Charles Burke, Daren Eugene Streett, Kevin Allen Sapp, Leslie Mark DeBruyne, Nabil Amir Rizk +2 more | 2013-01-08 |
| 8291202 | Apparatus and methods for speculative interrupt vector prefetching | Daren Eugene Streett | 2012-10-16 |
| 8185725 | Selective powering of a BHT in a processor having variable length instructions | Rodney Wayne Smith | 2012-05-22 |