Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12399837 | Translation lookaside buffer (TLB) prefetcher with multi-level TLB prefetches and feedback architecture | Benoy Alexander, Mohit Gopal Wani | 2025-08-26 |
| 12367154 | Logging guest physical address for memory access faults | Andrew Waterman | 2025-07-22 |
| 12066941 | Method for executing atomic memory operations when contested | Wesley Waylon Terpstra, Henry Cook, Leigang Kou | 2024-08-20 |
| 11847060 | Data cache with prediction hints for cache hits | Josh Smith | 2023-12-19 |
| 11687455 | Data cache with hybrid writeback and writethrough | Wesley Waylon Terpstra, Henry Cook | 2023-06-27 |
| 11620229 | Data cache with prediction hints for cache hits | Josh Smith | 2023-04-04 |
| 11467961 | Data cache with hybrid writeback and writethrough | Wesley Waylon Terpstra, Henry Cook | 2022-10-11 |
| 11467962 | Method for executing atomic memory operations when contested | Wesley Waylon Terpstra, Henry Cook, Leigang Kou | 2022-10-11 |
| 11023375 | Data cache with hybrid writeback and writethrough | Wesley Waylon Terpstra, Henry Cook | 2021-06-01 |
| 9329930 | Cache memory error detection circuits for detecting bit flips in valid indicators in cache memory following invalidate operations, and related methods and processor-based systems | Brian Michael Stempel, Thomas Philip Speier | 2016-05-03 |