Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12067338 | Multi version library cell handling and integrated circuit structures fabricated therefrom | Ranjith Kumar, Quan Shi, Mark Bohr, Andrew W. Yeoh, Sourav Chakravarty +1 more | 2024-08-20 |
| 11271010 | Multi version library cell handling and integrated circuit structures fabricated therefrom | Ranjith Kumar, Quan Shi, Mark Bohr, Andrew W. Yeoh, Sourav Chakravarty +1 more | 2022-03-08 |
| 11037923 | Through gate fin isolation | Mark Bohr, Stephen M. Cea | 2021-06-15 |
| 6721924 | Noise and power optimization in high performance circuits | Priyadarsan Patra | 2004-04-13 |
| 6721926 | Method and apparatus for improving digital circuit design | Xinning Wang, Prashant Sawkar | 2004-04-13 |
| 6556471 | VDD modulated SRAM for highly scaled, high performance cache | Ian A. Young | 2003-04-29 |
| 6279024 | High performance, low power incrementer for dynamic circuits | Terry I. Chappell, Sang Hoo Dhong, Mark S. Milshtein | 2001-08-21 |
| 5942917 | High speed ratioed CMOS logic structures for a pulsed input environment | Terry I. Chappell, Mark S. Milshtein, Thomas D. Fletcher | 1999-08-24 |
| 5748012 | Methodology to test pulsed logic circuits in pseudo-static mode | Michael P. Beakes, Terry I. Chappell, Bruce M. Fleischer, Rudolf A. Haring, Talal K. Jaber +1 more | 1998-05-05 |
| 5649170 | Interconnect and driver optimization for high performance processors | Parsotam T. Patel, Phoung Kim Phan, George Anthony Sai Halasz | 1997-07-15 |
| 5541427 | SRAM cell with capacitor | Bijan Davari, George A. Sai-Halasz, Yuan Taur | 1996-07-30 |
| 5542067 | Virtual multi-port RAM employing multiple accesses during single machine cycle | Terry I. Chappell, Mahmut K. Ebcioglu, Stanley E. Schuster | 1996-07-30 |
| 5471188 | Fast comparator circuit | Terry I. Chappell, Bruce M. Fleischer, Stanley E. Schuster | 1995-11-28 |
| 5204841 | Virtual multi-port RAM | Terry I. Chappell, Mahmut K. Ebcioglu, Stanley E. Schuster | 1993-04-20 |
| 5089726 | Fast cycle time clocked amplifier | Terry I. Chappell, Stanley E. Schuster | 1992-02-18 |
| 5015881 | High speed decoding circuit with improved AND gate | Terry I. Chappell, Stanley E. Schuster | 1991-05-14 |
| 4998028 | High speed CMOS logic device for providing ECL compatible logic levels | Terry I. Chappell, Stanley E. Schuster | 1991-03-05 |
| 4845677 | Pipelined memory chip structure having improved cycle time | Terry I. Chappell, Stanley E. Schuster | 1989-07-04 |
| 4843261 | Complementary output, high-density CMOS decoder/driver circuit for semiconductor memories | Terry I. Chappell, Stanley E. Schuster | 1989-06-27 |
| 4835419 | Source-follower emitter-coupled-logic receiver circuit | Terry I. Chappell, Stanley E. Schuster | 1989-05-30 |
| 4719372 | Multiplying interface circuit for level shifting between FET and TTL levels | Stanley E. Schuster | 1988-01-12 |
| 4697108 | Complementary input circuit with nonlinear front end and partially coupled latch | Stanley E. Schuster | 1987-09-29 |
| 4618784 | High-performance, high-density CMOS decoder/driver circuit | Thekkemadathil V. Rajeevakumar, Stanley E. Schuster, Lewis M. Terman | 1986-10-21 |
| 4583197 | Multi-stage pass transistor shifter/rotator | Hung-Hui Hsieh | 1986-04-15 |
| 4550489 | Heterojunction semiconductor | Terry I. Chappell, Jerry M. Woodall | 1985-11-05 |