Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10198333 | Test, validation, and debug architecture | Mark B. Trobough, Keshavan Tiruvallur, Chinna Prudvi, Christian Iovin, David W. Grawrock +37 more | 2019-02-05 |
| 8055697 | Method and device for dynamically verifying a processor architecture | — | 2011-11-08 |
| 6721924 | Noise and power optimization in high performance circuits | Barbara A. Chappell | 2004-04-13 |
| 6556962 | Method for reducing network costs and its application to domino circuits | — | 2003-04-29 |
| 6529861 | Power consumption reduction for domino circuits | Unni Krishnan Narayanan | 2003-03-04 |