Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5339274 | Variable bitline precharge voltage sensing technique for DRAM structures | Sang Hoo Dhong, Toshiaki Kirihata, Hyun Jong Shin, Toshio Sunaga, Yoichi Taira | 1994-08-16 |
| 5336629 | Folder Bitline DRAM having access transistors stacked above trench storage capacitors, each such transistor employing a planar semiconductor body which spans adjacent capacitors | Sang Hoo Dhong, Wei Hwang, Matthew R. Wordeman | 1994-08-09 |
| 5280452 | Power saving semsing circuits for dynamic random access memory | Sang Hoo Dhong | 1994-01-18 |
| 5214603 | Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors | Sang Hoo Dhong, Wei Hwang, Matthew R. Wordeman | 1993-05-25 |
| 5148059 | CMOS and ECL logic circuit requiring no interface circuitry | Chih-Liang Chen, Peter W. Cook | 1992-09-15 |
| 4763180 | Method and structure for a high density VMOS dynamic ram array | Wei Hwang, Stanley E. Schuster | 1988-08-09 |
| 4688063 | Dynamic ram cell with MOS trench capacitor in CMOS | Nicky C. Lu, Tak H. Ning | 1987-08-18 |
| 4638462 | Self-timed precharge circuit | Thekkemadathil V. Rajeevakumar | 1987-01-20 |
| 4618784 | High-performance, high-density CMOS decoder/driver circuit | Barbara A. Chappell, Thekkemadathil V. Rajeevakumar, Stanley E. Schuster | 1986-10-21 |
| 4326192 | Sequential successive approximation analog-to-digital converter | Richard B. Merrill, Yen S. Yee | 1982-04-20 |
| 4306300 | Multi-level charge-coupled device memory system including analog-to-digital and trigger comparator circuits | Yen S. Yee | 1981-12-15 |