Issued Patents All Time
Showing 176–200 of 211 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8914430 | Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions | Amit Gradstein, Cristina S. Anderson, Simon Rubanovich, Benny Eitan | 2014-12-16 |
| 8909988 | Recoverable parity and residue error | Ofer Levy, Michael Mishaeli, Ron Gabor | 2014-12-09 |
| 8879725 | Combining instructions including an instruction that performs a sequence of transformations to isolate one transformation | Shay Gueron | 2014-11-04 |
| 8706789 | Performing reciprocal instructions with high accuracy | Cristina S. Anderson, Benny Eitan, Simon Rubanovich, Amit Gradstein | 2014-04-22 |
| 8694758 | Mixing instructions with different register sizes | Doron Orenstien, Robert Valentine, Benny Eitan | 2014-04-08 |
| 8606841 | Method and apparatus for performing logical compare operation | Rajiv Kapoor, Ronen Zohar, Mark Buxton, Koby Gottlieb | 2013-12-10 |
| 8600049 | Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation | Shay Gueron, Amit Gradstein | 2013-12-03 |
| 8380780 | Method and apparatus for performing logical compare operations | Rajiv Kapoor, Ronen Zohar, Mark Buxton, Koby Gottlieb | 2013-02-19 |
| 8194854 | Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation | Shay Gueron, Amit Gradstein | 2012-06-05 |
| 8103858 | Efficient parallel floating point exception handling in a processor | Shachar Finkelstein, Gregory Pribush, Arnit Gradstein, Guy Bale, Thierry Pons | 2012-01-24 |
| 8082430 | Representing a plurality of instructions with a fewer number of micro-operations | Robert Valentine, Ittai Anati, Ido Ouziel, Gregory Pribush, Amir Leibovitz | 2011-12-20 |
| 8078836 | Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits | Robert Valentine, Benny Eitan, Doron Orenstein | 2011-12-13 |
| 7958181 | Method and apparatus for performing logical compare operations | Rajiv Kapoor, Ronen Zohar, Mark Buxton, Koby Gottlieb | 2011-06-07 |
| 7958336 | System and method for reservation station load dependency matrix | Sagi Lahav, Guy Patkin, Herbert Hum, Shih-Lien Linus Lu, Srikanth Srinivasan | 2011-06-07 |
| 7921280 | Selectively powered retirement unit using a partitioned allocation array and a partitioned writeback array | Rafi Marom, Ofer Levy | 2011-04-05 |
| 7882325 | Method and apparatus for a double width load using a single width load port | Robert Valentine, Ehud Cohen, Doron Orenstien, Benny Eitan | 2011-02-01 |
| 7721076 | Tracking an oldest processor event using information stored in a register and queue entry | Avinash Sodani, Vijaykumar B. Kadgi | 2010-05-18 |
| 7451294 | Apparatus and method for two micro-operation flow using source override | Yuval Bustan, Robert Valentine | 2008-11-11 |
| 7430656 | System and method of converting data formats and communicating between execution units | Ittai Anati, Oded Liron, Mohammad Abdallah | 2008-09-30 |
| 7389406 | Apparatus and methods for utilization of splittable execution units of a processor | Guillermo Savransky, Sagi Lahav | 2008-06-17 |
| 7365753 | Texture engine state variable synchronizer | Gabi Malka, Yael Shenhav | 2008-04-29 |
| 7213136 | Apparatus and method for redundant zero micro-operation removal | Robert Valentine | 2007-05-01 |
| 7206921 | Micro-operation un-lamination | Robert Valentine, Simcha Gochman | 2007-04-17 |
| 7202871 | Texture engine memory access synchronizer | Gavril Margittai, Gabi Malka | 2007-04-10 |
| 7167989 | Processor and methods to reduce power consumption of processor components | Ittai Anati, Ofer Sierra, Asi Joseph, Sagi Lahav | 2007-01-23 |