Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11455167 | Efficient implementation of complex vector fused multiply add and complex vector multiply | Raanan Sade, Amit Gradstein, Zeev Sperber, Mark J. Charney, Robert Valentine +1 more | 2022-09-27 |
| 10521226 | Efficient implementation of complex vector fused multiply add and complex vector multiply | Raanan Sade, Amit Gradstein, Zeev Sperber, Mark J. Charney, Robert Valentine +1 more | 2019-12-31 |
| 10157059 | Instruction and logic for early underflow detection and rounder bypass | Simon Rubanovich, Zeev Sperber, Amit Gradstein | 2018-12-18 |
| 9542154 | Fused multiply add operations using bit masks | Simon Rubanovich, Amit Gradstein, Zeev Sperber | 2017-01-10 |
| 9274752 | Leading change anticipator logic | Simon Rubanovich, Amit Gradstein, Zeev Sperber | 2016-03-01 |
| 9092226 | Efficient parallel floating point exception handling in a processor | Zeev Sperber, Shachar Finkelstein, Gregory Pribush, Amit Gradstein, Guy Bale | 2015-07-28 |
| 8918446 | Reducing power consumption in multi-precision floating point multipliers | Brent R. Boswell, Tom Aviram | 2014-12-23 |
| 8103858 | Efficient parallel floating point exception handling in a processor | Zeev Sperber, Shachar Finkelstein, Gregory Pribush, Arnit Gradstein, Guy Bale | 2012-01-24 |
| 7536485 | Processor having inactive state of operation and method thereof | Gila Kamhi, Zelig Wayner, Amit Gradstein, Yoad Yagil, Ittai Anati +1 more | 2009-05-19 |