Issued Patents All Time
Showing 25 most recent of 92 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11656875 | Method and system for instruction block to execution unit grouping | — | 2023-05-23 |
| 11467839 | Unified register file for supporting speculative architectural states | — | 2022-10-11 |
| 11294680 | Determining branch targets for guest branch instructions executed in native address space | — | 2022-04-05 |
| 11204769 | Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines | — | 2021-12-21 |
| 11163720 | Apparatus and method for processing an instruction matrix specifying parallel and dependent operations | — | 2021-11-02 |
| 11003459 | Method for implementing a line speed interconnect structure | — | 2021-05-11 |
| 10908913 | Method for a delayed branch implementation by using a front end track table | — | 2021-02-02 |
| 10740126 | Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation | Ankur Groen, Erika Gunadi, Mandeep Singh, Ravishankar Rao | 2020-08-11 |
| 10592300 | Method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization | — | 2020-03-17 |
| 10585670 | Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer | — | 2020-03-10 |
| 10585804 | Systems and methods for non-blocking implementation of cache flush instructions | Karthikeyan Avudaiyappan | 2020-03-10 |
| 10467010 | Method and apparatus for nearest potential store tagging | Mandeep Singh | 2019-11-05 |
| 10417000 | Method for a delayed branch implementation by using a front end track table | — | 2019-09-17 |
| 10394563 | Hardware accelerated conversion system using pattern matching | — | 2019-08-27 |
| 10372454 | Allocation of a segmented interconnect to support the execution of instruction sequences by a plurality of engines | — | 2019-08-06 |
| 10360031 | Fast unaligned memory access | Mandeep Singh | 2019-07-23 |
| 10353680 | System converter that implements a run ahead run time guest instruction conversion/decoding process and a prefetching process where guest code is pre-fetched from the target of guest branches in an instruction sequence | — | 2019-07-16 |
| 10346302 | Systems and methods for maintaining the coherency of a store coalescing cache and a load cache | Karthikeyan Avudaiyappan | 2019-07-09 |
| 10289419 | Method and apparatus for sorting elements in hardware structures | Mandeep Singh | 2019-05-14 |
| 10275255 | Method for dependency broadcasting through a source organized source view data structure | — | 2019-04-30 |
| 10255187 | Systems and methods for implementing weak stream software data and instruction prefetching using a hardware data prefetcher | Karthikeyan Avudaiyappan | 2019-04-09 |
| 10248570 | Methods, systems and apparatus for predicting the way of a set associative cache | Ravishankar Rao, Karthikeyan Avudaiyappan | 2019-04-02 |
| 10241795 | Guest to native block address mappings and management of native code storage | — | 2019-03-26 |
| 10228950 | Method and apparatus for guest return address stack emulation supporting speculation | — | 2019-03-12 |
| 10210101 | Systems and methods for flushing a cache with modified data | Karthikeyan Avudaiyappan | 2019-02-19 |