Issued Patents All Time
Showing 51–75 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9792212 | Virtual shared cache mechanism in a processing device | Aamer Jaleel, Bongjin Jung, Zeshan A. Chishti, Adrian C. Moga, Eric Delano +1 more | 2017-10-17 |
| 9727468 | Resolving multi-core shared cache access conflicts | Krishnakanth V. Sistla, George Cai, Jeffrey D. Gilbert | 2017-08-08 |
| 9727475 | Method and apparatus for distributed snoop filtering | Rahul Pal, Ishwar Agarwal, Joseph Nuzman, Ashok Jagannathan, Bahaa Fahim +1 more | 2017-08-08 |
| 9658963 | Speculative reads in buffered memory | Brian S. Morris, Bill Nale, Robert G. Blankenship | 2017-05-23 |
| 9647734 | Large-scale fading coefficient estimation in wireless massive MIMO systems | Ko-Feng Chen, York Ted Su | 2017-05-09 |
| 9639490 | Ring protocol for low latency interconnect switch | Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Bahaa Fahim, Ganapati Srinivasa | 2017-05-02 |
| 9626321 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2017-04-18 |
| 9619396 | Two level memory full line writes | Robert G. Blankenship, Jeffrey D. Chamberlain, Vedaraman Geetha | 2017-04-11 |
| 9606925 | Method, apparatus and system for optimizing cache memory transaction handling in a processor | Bahaa Fahim, Vedaraman Geetha, Jeffrey D. Chamberlain, Min Huang | 2017-03-28 |
| 9575895 | Providing common caching agent for core and integrated input/output (IO) module | Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Ganapati Srinivasa, Kenneth C. Creta, Sridhar Muthrasanallur +1 more | 2017-02-21 |
| 9471494 | Method and apparatus for cache line write back operation | Rajesh M. Sankaran, Neil Schaper, Joseph Nuzman, Larisa Novakovsky, Gilbert Neiger +1 more | 2016-10-18 |
| 9436605 | Cache coherency apparatus and method minimizing memory writeback operations | Jeffrey D. Chamberlain, Vedaraman Geetha, Robert G. Blankenship, Adrian C. Moga, Herbert Hum +1 more | 2016-09-06 |
| 9423959 | Method and apparatus for store durability and ordering in a persistent memory architecture | Subramanya R. Dulloor, Sanjay Kumar, Rajesh M. Sankaran, Gilbert Neiger, Richard Uhlig +7 more | 2016-08-23 |
| 9418009 | Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory | Adrian C. Moga, Vedaraman Geetha, Bahaa Fahim, Robert G. Blankenship, Jeffrey D. Chamberlain +1 more | 2016-08-16 |
| 9405687 | Method, apparatus and system for handling cache misses in a processor | Bahaa Fahim, Samuel D. Strom, Vedaraman Geetha, Robert G. Blankenship, Krishnakumar Ganapathy +1 more | 2016-08-02 |
| 9367112 | Optimizing power usage by factoring processor architectural events to PMU | P. Keong Or, Krishnakanth V. Sistla, Ganapati Srinivasa | 2016-06-14 |
| 9288260 | Apparatus, system, and methods for facilitating one-way ordering of messages | James Vash, Vida Vakilotojar, Bongjin Jung | 2016-03-15 |
| 9189296 | Caching agent for deadlock prevention in a processor by allowing requests that do not deplete available coherence resources | Bahaa Fahim, Jeffrey D. Chamberlain | 2015-11-17 |
| 8984228 | Providing common caching agent for core and integrated input/output (IO) module | Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Ganapati Srinivasa, Kenneth C. Creta, Sridhar Muthrasanallur +1 more | 2015-03-17 |
| 8966299 | Optimizing power usage by factoring processor architectural events to PMU | P Keong Or, Krishnakanth V. Sistla, Ganapati Srinivasa | 2015-02-24 |
| 8700933 | Optimizing power usage by factoring processor architectural events to PMU | P Keong Or, Krishnakanth V. Sistla, Ganapati Srinivasa | 2014-04-15 |
| 8645797 | Injecting a data error into a writeback path to memory | Theodros Yigzaw, Mohan J. Kumar, Jose A. Vargas | 2014-02-04 |
| 8554851 | Apparatus, system, and methods for facilitating one-way ordering of messages | James Vash, Vida Vakilotojar, Bongjin Jung | 2013-10-08 |
| 8473766 | Optimizing power usage by processor cores based on architectural events | P. Keong Or, Krishnakanth V. Sistla, Ganapati Srinivasa | 2013-06-25 |
| 8412970 | Optimizing power usage by factoring processor architectural events to PMU | P Keong Or, Krishnakanth V. Sistla, Ganapati Srinivasa | 2013-04-02 |