Issued Patents All Time
Showing 101–125 of 238 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10439134 | Techniques for forming non-planar resistive memory cells | Prashant Majhi, Elijah V. Karpov, Uday Shah, Charles C. Kuo, Ravi Pillarisetty +2 more | 2019-10-08 |
| 10424620 | Non-volatile memory devices including integrated ballast resistor | Prashant Majhi, Elijah V. Karpov, Ravi Pillarisetty, Uday Shah | 2019-09-24 |
| 10396211 | Functional metal oxide based microelectronic devices | Elijah V. Karpov, Prashant Majhi, Roza Kotlyar, Charles C. Kuo, Uday Shah +2 more | 2019-08-27 |
| 10388869 | Rare earth metal and metal oxide electrode interfacing of oxide memory element in resistive random access memory cell | Prashant Majhi, Elijah V. Karpov, Ravi Pillarisetty, Uday Shah, Brian S. Doyle +1 more | 2019-08-20 |
| 10355205 | Resistive memory cells including localized filamentary channels, devices including the same, and methods of making the same | Prashant Majhi, Ravi Pillarisetty, Uday Shah, Elijah V. Karpov, Brian S. Doyle +1 more | 2019-07-16 |
| 10340443 | Perpendicular magnetic memory with filament conduction path | Brian S. Doyle, Kaan Oguz, Kevin P. O'Brien, David L. Kencke, Elijah V. Karpov +5 more | 2019-07-02 |
| 10340275 | Stackable thin film memory | Elijah V. Karpov, Jack T. Kavalieros, Robert S. Chau, Rafael Rios, Prashant Majhi +5 more | 2019-07-02 |
| 10319646 | CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture | Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Jack T. Kavalieros, Willy Rachmady +4 more | 2019-06-11 |
| 10290614 | Group III-N transistors for system on chip (SOC) architecture integrating power management and radio frequency circuits | Han Wui Then, Robert S. Chau, Valluri Rao, Marko Radosavljevic, Ravi Pillarisetty +2 more | 2019-05-14 |
| 10275184 | Framework for volatile memory query execution in a multi node cluster | Vineet Marwah, Hui Jin, Kartik Kulkarni | 2019-04-30 |
| 10263074 | High voltage field effect transistors | Han Wui Then, Robert S. Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack T. Kavalieros +3 more | 2019-04-16 |
| 10249490 | Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy | Niti Goel, Robert S. Chau, Jack T. Kavalieros, Benjamin Chu-Kung, Matthew V. Metz +7 more | 2019-04-02 |
| 10236369 | Techniques for forming non-planar germanium quantum well devices | Ravi Pillarisetty, Jack T. Kavalieros, Willy Rachmady, Uday Shah, Benjamin Chu-Kung +4 more | 2019-03-19 |
| 10204135 | Materializing expressions within in-memory virtual column units to accelerate analytic queries | Aurosish Mishra, Shasank K. Chavan, Allison L. Holloway, Jesse Kamp, Ramesh Kumar +4 more | 2019-02-12 |
| 10186581 | Group III-N nanowire transistors | Han Wui Then, Robert S. Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack T. Kavalieros +3 more | 2019-01-22 |
| 10181518 | Selective epitaxially grown III-V materials based devices | Niti Goel, Gilbert Dewey, Matthew V. Metz, Marko Radosavljevic, Benjamin Chu-Kung +2 more | 2019-01-15 |
| 10177249 | Techniques for forming contacts to quantum well transistors | Ravi Pillarisetty, Benjamin Chu-Kung, Mantu K. Hudait, Marko Radosavljevic, Jack T. Kavalieros +2 more | 2019-01-08 |
| 10170612 | Epitaxial buffer layers for group III-N transistors on silicon substrates | Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Robert S. Chau | 2019-01-01 |
| 10133667 | Efficient data storage and retrieval using a heterogeneous main memory | Tirthankar Lahiri, Juan R. Loaiza, Jesse Kamp, Prashant Gaharwar, Hariharan Lakshmanan +1 more | 2018-11-20 |
| 10120895 | Mirroring, in memory, data from disk to improve query performance | Jesse Kamp, Amit Ganesh, Vineet Marwah, Vivekanandhan Raja, Tirthankar Lahiri +6 more | 2018-11-06 |
| 10103263 | Strained channel region transistors employing source and drain stressors and systems including the same | Van H. Le, Harold W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros | 2018-10-16 |
| 10096474 | Methods and structures to prevent sidewall defects during selective epitaxy | Niti Goel, Sanaz K. Gardner, Pragyansri Pathi, Matthew V. Metz, Sansaptak Dasgupta +6 more | 2018-10-09 |
| 10096709 | Aspect ratio trapping (ART) for fabricating vertical semiconductor devices | Van H. Le, Benjamin Chu-Kung, Gilbert Dewey, Jack T. Kavalieros, Ravi Pillarisetty +4 more | 2018-10-09 |
| 10090461 | Oxide-based three-terminal resistive switching logic devices | Elijah V. Karpov, Prashant Majhi, Ravi Pillarisetty, Brian S. Doyle, Uday Shah +1 more | 2018-10-02 |
| 10074718 | Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack | Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Benjamin Chu-Kung | 2018-09-11 |