Issued Patents All Time
Showing 601–625 of 625 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7037845 | Selective etch process for making a semiconductor device having a high-k gate dielectric | Justin K. Brask, Uday Shah, Mark L. Doczy, Robert S. Chau, Robert Turkot +1 more | 2006-05-02 |
| 7005366 | Tri-gate devices and methods of fabrication | Robert S. Chau, Brian S. Doyle, Douglas Barlage, Suman Datta, Scott A. Hareland | 2006-02-28 |
| 6998686 | Metal-gate electrode for CMOS transistor applications | Robert S. Chau, Mark L. Doczy, Brian S. Doyle | 2006-02-14 |
| 6974764 | Method for making a semiconductor device having a metal gate electrode | Justin K. Brask, Mark L. Doczy, Uday Shah, Matthew V. Metz, Robert S. Chau +1 more | 2005-12-13 |
| 6974733 | Double-gate transistor with enhanced carrier mobility | Boyan Boyanov, Brian S. Doyle, Anand S. Murthy, Robert S. Chau | 2005-12-13 |
| 6972225 | integrating n-type and P-type metal gate transistors | Mark L. Doczy, Justin K. Brask, Steven J. Keating, Chris Barns, Brian S. Doyle +2 more | 2005-12-06 |
| 6970373 | Method and apparatus for improving stability of a 6T CMOS SRAM cell | Suman Datta, Brian S. Doyle, Robert S. Chau, Bo Zheng, Scott A. Hareland | 2005-11-29 |
| 6960517 | N-gate transistor | Rafael Rios, Brian S. Doyle, Thomas D. Linton | 2005-11-01 |
| 6953719 | Integrating n-type and p-type metal gate transistors | Mark L. Doczy, Justin K. Brask, Steven J. Keating, Chris Barns, Brian S. Doyle +2 more | 2005-10-11 |
| 6952040 | Transistor structure and method of fabrication | Robert S. Chau, Anand S. Murthy, Brian Roberds, Brian S. Doyle | 2005-10-04 |
| 6939815 | Method for making a semiconductor device having a high-k gate dielectric | Justin K. Brask, Mark L. Doczy, Scott A. Hareland, John Barnak, Matthew V. Metz +1 more | 2005-09-06 |
| 6914295 | Tri-gate devices and methods of fabrication | Robert S. Chau, Brian S. Doyle, Douglas Barlage, Suman Datta, Scott A. Hareland | 2005-07-05 |
| 6893927 | Method for making a semiconductor device with a metal gate electrode | Uday Shah, Mark L. Doczy, Justin K. Brask, Matthew V. Metz, Robert S. Chau | 2005-05-17 |
| 6887800 | Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction | Matthew V. Metz, Suman Datta, Mark L. Doczy, Justin K. Brask, Uday Shah +1 more | 2005-05-03 |
| 6869889 | Etching metal carbide films | Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah +2 more | 2005-03-22 |
| 6858478 | Tri-gate devices and methods of fabrication | Robert S. Chau, Brian S. Doyle, Douglas Barlage, Suman Datta, Scott A. Hareland | 2005-02-22 |
| 6858483 | Integrating n-type and p-type metal gate transistors | Mark L. Doczy, Justin K. Brask, Steven J. Keating, Chris Barns, Brian S. Doyle +2 more | 2005-02-22 |
| 6808993 | Ultra-thin gate dielectrics | Christine M. Finnie, Pauline Jacob, Nick Lindert, Keith Matthew Jackson, Kirk Althoff +2 more | 2004-10-26 |
| 6784491 | MOS devices with reduced fringing capacitance | Brian S. Doyle | 2004-08-31 |
| 6696345 | Metal-gate electrode for CMOS transistor applications | Robert S. Chau, Mark L. Doczy, Brian S. Doyle | 2004-02-24 |
| 6667232 | Thin dielectric layers and non-thermal formation thereof | Steven J. Keating, Robert S. Chau, Reza Arghavani, Douglas Barlage | 2003-12-23 |
| 6667251 | Plasma nitridation for reduced leakage gate dielectric layers | Robert McFadden, Reza Arghavani, Doug Barlage, Robert S. Chau | 2003-12-23 |
| 6653700 | Transistor structure and method of fabrication | Robert S. Chau, Anand S. Murthy, Brian Roberds, Brian S. Doyle | 2003-11-25 |
| 6610615 | Plasma nitridation for reduced leakage gate dielectric layers | Robert McFadden, Reza Arghavani, Doug Barlage, Robert S. Chau | 2003-08-26 |
| 6124171 | Method of forming gate oxide having dual thickness by oxidation process | Reza Arghavani, Bruce Beattie, Robert S. Chau, Bob McFadden | 2000-09-26 |