Issued Patents All Time
Showing 551–575 of 625 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7427541 | Carbon nanotube energy well (CNEW) field effect transistor | Suman Datta, Marko Radosavljevic, Brian S. Doyle, Justin K. Brask, Amlan Majumdar +1 more | 2008-09-23 |
| 7425500 | Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors | Matthew V. Metz, Suman Datta, Mark L. Doczy, Justin K. Brask, Robert S. Chau | 2008-09-16 |
| 7425490 | Reducing reactions between polysilicon gate electrodes and high dielectric constant gate dielectrics | Justin K. Brask, Mark L. Doczy, Uday Shah, Matthew V. Metz, Suman Datta +1 more | 2008-09-16 |
| 7422971 | Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby | Anand S. Murthy, Brian S. Doyle, Robert S. Chau | 2008-09-09 |
| 7422936 | Facilitating removal of sacrificial layers via implantation to form replacement metal gates | Chris Barns, Matt Prince, Mark L. Doczy, Justin K. Brask | 2008-09-09 |
| 7402875 | Lateral undercut of metal gate in SOI device | Suman Datta, Justin K. Brask, Brian S. Doyle, Gilbert Dewey, Mark L. Doczy +1 more | 2008-07-22 |
| 7402856 | Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same | Justin K. Brask, Brian S. Doyle, Robert S. Chau | 2008-07-22 |
| 7390947 | Forming field effect transistors from conductors | Amlan Majumdar, Justin K. Brask, Marko Radosavljevic, Suman Datta, Brian S. Doyle +5 more | 2008-06-24 |
| 7390709 | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode | Mark L. Doczy, Justin K. Brask, Uday Shah, Matthew V. Metz, Suman Datta +2 more | 2008-06-24 |
| 7387927 | Reducing oxidation under a high K gate dielectric | Robert Turkot, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Uday Shah +2 more | 2008-06-17 |
| 7384880 | Method for making a semiconductor device having a high-k gate dielectric | Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Robert S. Chau | 2008-06-10 |
| 7381608 | Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode | Justin K. Brask, Sangwoo Pae, Matthew V. Metz, Mark L. Doczy, Suman Datta +2 more | 2008-06-03 |
| 7361958 | Nonplanar transistors with metal gate electrodes | Justin K. Brask, Brian S. Doyle, Mark L. Doczy, Uday Shah, Robert S. Chau | 2008-04-22 |
| 7358121 | Tri-gate devices and methods of fabrication | Robert S. Chau, Brian S. Doyle, Douglas Barlage, Suman Datta | 2008-04-15 |
| 7355281 | Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode | Justin K. Brask, Mark L. Doczy, Uday Shah, Chris Barns, Matthew V. Metz +3 more | 2008-04-08 |
| 7355254 | Pinning layer for low resistivity N-type source drain ohmic contacts | Suman Datta, Robert S. Chau, Mark L. Doczy | 2008-04-08 |
| 7354832 | Tri-gate device with conformal PVD workfunction metal on its three-dimensional body and fabrication method thereof | Willy Rachmady, Brian S. Doyle, Uday Shah | 2008-04-08 |
| 7323423 | Forming high-k dielectric layers on smooth substrates | Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah +2 more | 2008-01-29 |
| 7316949 | Integrating n-type and p-type metal gate transistors | Mark L. Doczy, Justin K. Brask, Steven J. Keating, Chris Barns, Brian S. Doyle +2 more | 2008-01-08 |
| 7317231 | Method for making a semiconductor device having a high-K gate dielectric and a titanium carbide gate electrode | Matthew V. Metz, Suman Datta, Mark L. Doczy, Justin K. Brask, Robert S. Chau | 2008-01-08 |
| 7279375 | Block contact architectures for nanoscale channel transistors | Marko Radosavljevic, Amlan Majumdar, Brian S. Doyle, Mark L. Doczy, Justin K. Brask +3 more | 2007-10-09 |
| 7235809 | Semiconductor channel on insulator structure | Been-Yih Jin, Brian S. Doyle, Scott A. Hareland, Mark L. Doczy, Matthew V. Metz +3 more | 2007-06-26 |
| 7220635 | Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer | Justin K. Brask, Mark L. Doczy, Uday Shah, Matthew V. Metz, Chris Barns +3 more | 2007-05-22 |
| 7217611 | Methods for integrating replacement metal gate structures | Justin K. Brask, Mark L. Doczy, Scott A. Hareland, Matthew V. Metz, Chris Barns +1 more | 2007-05-15 |
| 7217644 | Method of manufacturing MOS devices with reduced fringing capacitance | Brian S. Doyle | 2007-05-15 |