Issued Patents All Time
Showing 51–75 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10497814 | III-V semiconductor alloys for use in the subfin of non-planar semiconductor devices and methods of forming the same | Matthew V. Metz, Willy Rachmady, Gilbert Dewey, Chandra S. Mohapatra, Anand S. Murthy +2 more | 2019-12-03 |
| 10446685 | High-electron-mobility transistors with heterojunction dopant diffusion barrier | Chandra S. Mohapatra, Matthew V. Metz, Gilbert Dewey, Willy Rachmady, Anand S. Murthy +2 more | 2019-10-15 |
| 10388764 | High-electron-mobility transistors with counter-doped dopant diffusion barrier | Chandra S. Mohapatra, Matthew V. Metz, Gilbert Dewey, Willy Rachmady, Anand S. Murthy +2 more | 2019-08-20 |
| 10243078 | Carrier confinement for high mobility channel devices | Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Tahir Ghani +3 more | 2019-03-26 |
| 10229997 | Indium-rich NMOS transistor channels | Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Tahir Ghani, Willy Rachmady +3 more | 2019-03-12 |
| 10186580 | Semiconductor device having germanium active layer with underlying diffusion barrier layer | Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jack T. Kavalieros, Robert S. Chau | 2019-01-22 |
| 10170314 | Pulsed laser anneal process for transistor with partial melt of a raised source-drain | Jacob Jensen, Tahir Ghani, Mark Liu, Robert James | 2019-01-01 |
| 10153372 | High mobility strained channels for fin-based NMOS transistors | Stephen M. Cea, Roza Kotlyar, Glenn A. Glass, Anand S. Murthy, Willy Rachmady +1 more | 2018-12-11 |
| 10109711 | CMOS FinFET device having strained SiGe fins and a strained Si cladding layer on the NMOS channel | Stephen M. Cea, Roza Kotlyar, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn +1 more | 2018-10-23 |
| 10103263 | Strained channel region transistors employing source and drain stressors and systems including the same | Van H. Le, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros, Niloy Mukherjee | 2018-10-16 |
| 9966440 | Tin doped III-V material contacts | Glenn A. Glass, Anand S. Murthy, Michael Jackson | 2018-05-08 |
| 9935107 | CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the same | Stephen M. Cea, Roza Kotlyar, Kelin J. Kuhn, Tahir Ghani | 2018-04-03 |
| 9905651 | GE and III-V channel semiconductor devices having maximized compliance and free surface relaxation | Ravi Pillarisetty, Sansaptak Dasgupta, Niti Goel, Van H. Le, Marko Radosavljevic +8 more | 2018-02-27 |
| 9818884 | Strain compensation in transistors | Van H. Le, Benjamin Chu-Kung, Jack T. Kavalieros, Ravi Pillarisetty, Willy Rachmady | 2017-11-14 |
| 9698265 | Strained channel region transistors employing source and drain stressors and systems including the same | Van H. Le, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros, Niloy Mukherjee | 2017-07-04 |
| 9608055 | Semiconductor device having germanium active layer with underlying diffusion barrier layer | Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jack T. Kavalieros, Robert S. Chau | 2017-03-28 |
| 9570614 | Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation | Ravi Pillarisetty, Sansaptak Dasgupta, Niti Goel, Van H. Le, Marko Radosavljevic +8 more | 2017-02-14 |
| 9443980 | Pulsed laser anneal process for transistors with partial melt of a raised source-drain | Jacob Jensen, Tahir Ghani, Mark Liu, Robert James | 2016-09-13 |
| 9397166 | Strained channel region transistors employing source and drain stressors and systems including the same | Van H. Le, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros, Niloy Mukherjee | 2016-07-19 |
| 9240322 | Method for forming superactive deactivation-resistant junction with laser anneal and multiple implants | Jacob Jensen, Tahir Ghani, Robert James, Mark Liu | 2016-01-19 |
| 9196704 | Selective laser annealing process for buried regions in a MOS device | Jacob Jensen, Tahir Ghani, Mark Liu, Robert James | 2015-11-24 |
| 9006069 | Pulsed laser anneal process for transistors with partial melt of a raised source-drain | Jacob Jensen, Tahir Ghani, Mark Liu, Robert James | 2015-04-14 |
| 8896066 | Tin doped III-V material contacts | Glenn A. Glass, Anand S. Murthy, Michael Jackson | 2014-11-25 |
| 7892971 | Sub-second annealing processes for semiconductor devices | Jack Hwang, Sridhar Govindaraju, Karson Knutson, Aravind S. Killampalli | 2011-02-22 |
| 7758238 | Temperature measurement with reduced extraneous infrared in a processing chamber | Sridhar Govindaraju, Karson Knutson, Aravind S. Killampalli, Jack Hwang | 2010-07-20 |