Issued Patents All Time
Showing 51–74 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7494915 | Back end interconnect with a shaped interface | Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor +8 more | 2009-02-24 |
| 7436016 | MIM capacitor with a cap layer over the conductive plates | Hans-Joachim Barth, Petra Felsner, Gerald Friese | 2008-10-14 |
| 7368804 | Method and apparatus of stress relief in semiconductor structures | Mark Hoinkis, Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner | 2008-05-06 |
| 7332812 | Memory card with connecting portions for connection to an adapter | Klaus Herold | 2008-02-19 |
| 7307346 | Final passivation scheme for integrated circuits | Christian Pils | 2007-12-11 |
| 7268383 | Capacitor and method of manufacturing a capacitor | Petra Felsner, Thomas Schafbauer, Uwe Kerst, Hans-Joachim Barth | 2007-09-11 |
| 7241681 | Bilayered metal hardmasks for use in dual damascene etch schemes | Kaushik A. Kumar, Lawrence A. Clevenger, Timothy J. Dalton, Douglas C. La Tulipe, Jr., Andy Cowley +5 more | 2007-07-10 |
| 7201634 | Polishing methods and apparatus | Markus Naujok | 2007-04-10 |
| 7125792 | Dual damascene structure and method | Kaushik A. Kumar, Douglas C. La Tulipe, Jr., Timothy J. Dalton, Larry Clevenger, Andy Cowley +1 more | 2006-10-24 |
| 7122462 | Back end interconnect with a shaped interface | Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor +8 more | 2006-10-17 |
| 7091612 | Dual damascene structure and method | Kaushik A. Kumar, Timothy J. Dalton, Larry Clevenger, Andy Cowley, Douglas C. La Tulipe, Jr. +5 more | 2006-08-15 |
| 7060619 | Reduction of the shear stress in copper via's in organic interlayer dielectric material | Andy Cowley, Mark Hoinkis, Michael Stetter | 2006-06-13 |
| 7052621 | Bilayered metal hardmasks for use in Dual Damascene etch schemes | Kaushik A. Kumar, Lawrence A. Clevenger, Timothy J. Dalton, Douglas C. La Tulipe, Jr., Andy Cowley +5 more | 2006-05-30 |
| 6960835 | Stress-relief layer for semiconductor applications | Hans-Joachim Barth, Mark Hoinkis, Gerald Friese, Pak K. Leung | 2005-11-01 |
| 6949442 | Methods of forming MIM capacitors | Hans-Joachim Barth, Petra Felsner, Gerald Friese | 2005-09-27 |
| 6914320 | Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof | Tze-Chiang Chen, Brett H. Engel, John A. Fitzsimmons, Terence L. Kane, Naftall E. Lustig +5 more | 2005-07-05 |
| 6887783 | Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof | Tze-Chiang Chen, Brett H. Engel, John A. Fitzsimmons, Terence L. Kane, Naftall E. Lustig +5 more | 2005-05-03 |
| 6806182 | Method for eliminating via resistance shift in organic ILD | Darryl D. Restaino, Shahab Siddiqui, Delores Bennett, Chih-Chih Liu, Hsueh-Chung Chen +3 more | 2004-10-19 |
| 6806579 | Robust via structure and method | Andy Cowley, Michael Stetter | 2004-10-19 |
| 6730982 | FBEOL process for Cu metallizations free from Al-wirebond pads | Hans-Joachim Barth, Petra Felsner, Gerald Friese | 2004-05-04 |
| 6638851 | Dual hardmask single damascene integration scheme in an organic low k ILD | Andy Cowley, Michael Stetter | 2003-10-28 |
| 6613664 | Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices | Hans-Joachin Barth | 2003-09-02 |
| 6387754 | Method of forming an on-chip decoupling capacitor with bottom hardmask | Timothy J. Dalton, Andrew P. Cowley, Peter A. Emmi, Vincent J. McGahay | 2002-05-14 |
| 6278147 | On-chip decoupling capacitor with bottom hardmask | Timothy J. Dalton, Andrew P. Cowley, Peter A. Emmi, Vincent J. McGahay | 2001-08-21 |