Issued Patents All Time
Showing 376–400 of 414 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7890731 | Clearing selected storage translation buffer entries based on table origin address | Lisa C. Heller, Erwin Pfeffer, Kenneth E. Plambeck | 2011-02-15 |
| 7870339 | Extract cache attribute facility and instruction therefore | Dan F. Greiner | 2011-01-11 |
| 7814374 | System and method for the capture and preservation of intermediate error state data | Douglas G. Balazich, Michael Billeci, Anthony Saporito | 2010-10-12 |
| 7805634 | Error accumulation register, error accumulation method, and error accumulation system | Douglas G. Balazich, Michael Billeci, Anthony Saporito | 2010-09-28 |
| 7739545 | System and method to support use of bus spare wires in connection modules | Mark A. Check, Jonathan Y. Chen, Thomas G. Foote | 2010-06-15 |
| 7712076 | Register indirect access of program floating point registers by millicode | Steven R. Carlough, Mark S. Farrell, Eric M. Schwarz, Charles F. Webb | 2010-05-04 |
| 7530067 | Filtering processor requests based on identifiers | Lisa C. Heller, Erwin Pfeffer, Ute Gaertner | 2009-05-05 |
| 7434035 | Method and system for processing instructions in grouped and non-grouped modes | Fadi Y. Busaba | 2008-10-07 |
| 7284100 | Invalidating storage, clearing buffer entries, and an instruction therefor | Lisa C. Heller, Erwin Pfeffer, Kenneth E. Plambeck | 2007-10-16 |
| 7278063 | Method and system for performing a hardware trace | Michael Billeci | 2007-10-02 |
| 7200742 | System and method for creating precise exceptions | Fadi Y. Busaba, Michael J. Mack, John G. Rell, Jr., Eric M. Schwarz, Chung-Lung K. Shum +2 more | 2007-04-03 |
| 7197601 | Method, system and program product for invalidating a range of selected storage translation table entries | Lisa C. Heller, Erwin Pfeffer, Kenneth E. Plambeck | 2007-03-27 |
| 7111196 | System and method for providing processor recovery in a multi-core system | Douglas G. Balazich, Michael Billeci, Anthony Saporito | 2006-09-19 |
| 7103754 | Computer instructions for having extended signed displacement fields for finding instruction operands | Mark A. Check, Brian B. Moore | 2006-09-05 |
| 7085917 | Multi-pipe dispatch and execution of complex instructions in a superscalar processor | Fadi Y. Busaba, Steven R. Carlough, Christopher A. Krygowski, John G. Rell, Jr. | 2006-08-01 |
| 7082550 | Method and apparatus for mirroring units within a processor | Michael Billeci, Chung-Lung K. Shum | 2006-07-25 |
| 7082517 | Superscalar microprocessor having multi-pipe dispatch and execution unit | Fadi Y. Busaba, Klaus J. Getzlaff, Christopher A. Krygowski | 2006-07-25 |
| 7035986 | System and method for simultaneous access of the same line in cache storage | Mark A. Check, Jennifer A. Navarro, Chung-Lung K. Shum, Aaron Tsai | 2006-04-25 |
| 7010676 | Last iteration loop branch prediction upon counter threshold and resolution upon counter one | Fadi Y. Busaba, Klaus J. Getzlaff, Christopher A. Krygowski | 2006-03-07 |
| 6996698 | Blocking processing restrictions based on addresses | Jane H. Bartik, Lisa C. Heller, Erwin Pfeffer, Ute Gaertner | 2006-02-07 |
| 6189112 | Transparent processor sparing | Robert E. Murray | 2001-02-13 |
| 6178495 | Processor E-unit to I-unit interface instruction modification with E-unit opcode computer logic in the unit | Mark A. Check | 2001-01-23 |
| 6125444 | Millimode capable computer system providing global branch history table disables and separate millicode disables which enable millicode disable to be turned off for some sections of code execution but not disabled for all | Mark A. Check, John S. Liptay, Charles F. Webb, Mark S. Farrell | 2000-09-26 |
| 6119219 | System serialization with early release of individual processor | Charles F. Webb, Dean G. Bair, Mark S. Farrell, Barry W. Krumm, Pak-kin Mak +1 more | 2000-09-12 |
| 6115829 | Computer system with transparent processor sparing | Robert E. Murray | 2000-09-05 |