TS

Timothy J. Slegel

IBM: 414 patents #39 of 70,183Top 1%
📍 Staatsburg, NY: #1 of 55 inventorsTop 2%
🗺 New York: #29 of 115,490 inventorsTop 1%
Overall (All Time): #582 of 4,157,543Top 1%
414
Patents All Time

Issued Patents All Time

Showing 351–375 of 414 patents

Patent #TitleCo-InventorsDate
8447949 Detection of zero address events in address formation Robert M. Abrams, Mark S. Farrell, Dan F. Greiner, Christian Jacobi, James H. Mulder +2 more 2013-05-21
8417916 Perform frame management function instruction for setting storage keys and clearing blocks of main storage Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Gustav E. Sittmann, III 2013-04-09
8407453 Facilitating processing in a computing environment using an extended drain instruction Khary J. Alexander, Fadi Y. Busaba, Mark S. Farrell, Bruce C. Giamei, Charles F. Webb 2013-03-26
8381040 Relocatable interrupt handler for test generation and execution Eli Almog 2013-02-19
8335906 Perform frame management function instruction for clearing blocks of main storage Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Gustav E. Sittmann, III 2012-12-18
8332614 System, method and computer program product for providing a programmable quiesce filtering register Lisa C. Heller, Harald Boehm, Ute Gaertner, Jennifer A. Navarro 2012-12-11
8234642 Filtering processor requests based on identifiers Lisa C. Heller, Erwin Pfeffer, Ute Gaertner 2012-07-31
8151083 Dynamic address translation with frame management Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Gustav E. Sittmann, III 2012-04-03
8140834 System, method and computer program product for providing a programmable quiesce filtering register Lisa C. Heller, Harald Boehm, Ute Gaertner, Jennifer A. Navarro 2012-03-20
8131934 Extract cache attribute facility and instruction therefore Dan F. Greiner 2012-03-06
8122195 Instruction for pre-fetching data and releasing cache lines Dan F. Greiner 2012-02-21
8122224 Clearing selected storage translation buffer entries bases on table origin address Lisa C. Heller, Erwin Pfeffer, Kenneth E. Plambeck 2012-02-21
8117417 Dynamic address translation with change record override Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Charles F. Webb 2012-02-14
8103851 Dynamic address translation with translation table entry format control for indentifying format of the translation table entry Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Charles F. Webb 2012-01-24
8095821 Debugging for multiple errors in a microprocessor environment Ulrich Mayer, Chung-Lung K. Shum, Frank Lehnert, Guenter Gerwig 2012-01-10
8082405 Dynamic address translation with fetch protection Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer +1 more 2011-12-20
8078843 Facilitating processing in a computing environment using an extended drain instruction Khary J. Alexander, Fadi Y. Busaba, Mark S. Farrell, Bruce C. Giamei, Charles F. Webb 2011-12-13
8041922 Enhanced dynamic address translation with load real address function Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Gustav E. Sittmann, III 2011-10-18
8041923 Load page table entry address instruction execution based on an address translation format control field Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Gustav E. Sittmann, III 2011-10-18
8037278 Dynamic address translation with format control Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Charles F. Webb 2011-10-11
8019964 Dynamic address translation with DAT protection Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer +1 more 2011-09-13
7984276 Method and system for altering processor execution of a group of instructions Fadi Y. Busaba 2011-07-19
7921279 Operand and result forwarding between differently sized operands in a superscalar processor David S. Hutton, Fadi Y. Busaba, Bruce C. Giamei, Christopher A. Krygowski, Edward T. Malley +3 more 2011-04-05
7908518 Method, system and computer program product for failure analysis implementing automated comparison of multiple reference models Patrick M. West, Jr., Vimal M. Kapadia, Christopher A. Krygowski 2011-03-15
7895419 Rotate then operate on selected bits facility and instructions therefore Dan F. Greiner, Joachim von Buttlar 2011-02-22