TS

Timothy J. Slegel

IBM: 414 patents #39 of 70,183Top 1%
📍 Staatsburg, NY: #1 of 55 inventorsTop 2%
🗺 New York: #29 of 115,490 inventorsTop 1%
Overall (All Time): #582 of 4,157,543Top 1%
414
Patents All Time

Issued Patents All Time

Showing 301–325 of 414 patents

Patent #TitleCo-InventorsDate
9329861 Convert to zoned format from decimal floating point format Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz 2016-05-03
9317460 Program event recording within a transactional environment Dan F. Greiner, Christian Jacobi, Damian L. Osisek 2016-04-19
9311101 Intra-instructional transaction abort handling Brenton F. Belmar, Mark S. Farrell, Christian Jacobi 2016-04-12
9311259 Program event recording within a transactional environment Dan F. Greiner, Christian Jacobi, Damian L. Osisek 2016-04-12
9292443 Multilevel cache system Khary J. Alexander, Christian Jacobi, Martin Recktenwald 2016-03-22
9292453 Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB) Khary J. Alexander, Jonathan T. Hsieh, Christian Jacobi 2016-03-22
9286076 Intra-instructional transaction abort handling Brenton F. Belmar, Mark S. Farrell, Christian Jacobi 2016-03-15
9280448 Controlling operation of a run-time instrumentation facility from a lesser-privileged state Mark S. Farrell, Charles W. Gainey, Jr., Marcel Mitran, Chung-Lung K. Shum, Brian L. Smith +1 more 2016-03-08
9280447 Modifying run-time-instrumentation controls from a lesser-privileged state Mark S. Farrell, Charles W. Gainey, Jr., Chung-Lung K. Shum 2016-03-08
9274957 Monitoring a value in storage without repeated storage access Khary J. Alexander, Ute Gaertner, Jonathan T. Hsieh, Christian Jacobi 2016-03-01
9268566 Character data match determination by loading registers at most up to memory block boundary and comparing Jonathan D. Bradbury, Michael K. Gschwind 2016-02-23
9262206 Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments Harold W. Cain, III, Maged M. Michael, Chung-Lung K. Shum 2016-02-16
9262207 Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments Harold W. Cain, III, Maged M. Michael, Chung-Lung K. Shum 2016-02-16
9223574 Start virtual execution instruction for dispatching multiple threads in a computer Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +5 more 2015-12-29
9218442 Firmware and hardware verification using Opcode comparison Christopher A. Krygowski, Michael P. Mullen, Kai Weber 2015-12-22
9218288 Monitoring a value in storage without repeated storage access Khary J. Alexander, Ute Gaertner, Jonathan T. Hsieh, Christian Jacobi 2015-12-22
9218185 Multithreading capability information retrieval Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more 2015-12-22
9207706 Generating monotonically increasing TOD values in a multiprocessor system Guenter Gerwig, Christian Jacobi, Frank Lehnert, Chung-Lung K. Shum 2015-12-08
9164911 Atomic execution over accesses to multiple memory locations in a multiprocessor system Mark S. Farrell, Jonathan T. Hsieh, Christian Jacobi 2015-10-20
9158711 Creating a program product or system for executing a perform frame management instruction Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Gustav E. Sittmann, III 2015-10-13
9158660 Controlling operation of a run-time instrumentation facility Mark S. Farrell, Charles W. Gainey, Jr., Marcel Mitran, Chung-Lung K. Shum, Brian L. Smith +1 more 2015-10-13
9146739 Branch prediction preloading James J. Bonanno, Marcel Mitran, Brian R. Prasky, Joran S. C. Siu, Alexander Vasilevskiy 2015-09-29
9146740 Branch prediction preloading James J. Bonanno, Marcel Mitran, Brian R. Prasky, Joran S. C. Siu, Alexander Vasilevskiy 2015-09-29
9135004 Rotate then operate on selected bits facility and instructions therefor Dan F. Greiner, Joachim von Buttlar 2015-09-15
9069675 Creating a program product or system for executing an instruction for pre-fetching data and releasing cache lines Dan F. Greiner 2015-06-30