Issued Patents All Time
Showing 326–350 of 414 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9052889 | Load pair disjoint facility and instruction therefor | Christian Jacobi, Marcel Mitran, Charles F. Webb | 2015-06-09 |
| 9021225 | Dynamic address translation with fetch protection in an emulated environment | Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer +1 more | 2015-04-28 |
| 9003134 | Emulation of a dynamic address translation with change record override on a machine of another architecture | Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Charles F. Webb | 2015-04-07 |
| 8977823 | Store buffer for transactional memory | Khary J. Alexander, Christian Jacobi, Gerrit Koch, Martin Recktenwald, Hans-Werner Tast | 2015-03-10 |
| 8966324 | Transactional execution branch indications | Dan F. Greiner, Christian Jacobi, Donald W. Schmidt | 2015-02-24 |
| 8930673 | Load page table entry address instruction execution based on an address translation format control field | Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Gustav E. Sittmann, III | 2015-01-06 |
| 8914619 | High-word facility for extending the number of general purpose registers available to instructions | Dan F. Greiner, Marcel Mitran | 2014-12-16 |
| 8909899 | Emulating execution of a perform frame management instruction | Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Gustav E. Sittmann, III | 2014-12-09 |
| 8887003 | Transaction diagnostic block | Dan F. Greiner, Christian Jacobi, Marcel Mitran | 2014-11-11 |
| 8887002 | Transactional execution branch indications | Dan F. Greiner, Christian Jacobi, Donald W. Schmidt | 2014-11-11 |
| 8880959 | Transaction diagnostic block | Dan F. Greiner, Christian Jacobi, Marcel Mitran | 2014-11-04 |
| 8850166 | Load pair disjoint facility and instruction therefore | Christian Jacobi, Marcel Mitran, Charles F. Webb | 2014-09-30 |
| 8838943 | Rotate then operate on selected bits facility and instructions therefore | Dan F. Greiner, Joachim von Buttlar | 2014-09-16 |
| 8806179 | Non-quiescing key setting facility | Dan F. Greiner, Christian Jacobi, Chung-Lung K. Shum | 2014-08-12 |
| 8799583 | Atomic execution over accesses to multiple memory locations in a multiprocessor system | Mark S. Farrell, Jonathan T. Hsieh, Christian Jacobi | 2014-08-05 |
| 8751775 | Non-quiescing key setting facility | Dan F. Greiner, Christian Jacobi, Chung-Lung K. Shum | 2014-06-10 |
| 8688661 | Transactional processing | Dan F. Greiner, Christian Jacobi | 2014-04-01 |
| 8682877 | Constrained transaction execution | Dan F. Greiner, Christian Jacobi | 2014-03-25 |
| 8683138 | Instruction for pre-fetching data and releasing cache lines | Dan F. Greiner | 2014-03-25 |
| 8677098 | Dynamic address translation with fetch protection | Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer +1 more | 2014-03-18 |
| 8639911 | Load page table entry address instruction execution based on an address translation format control field | Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Gustav E. Sittmann, III | 2014-01-28 |
| 8621180 | Dynamic address translation with translation table entry format control for identifying format of the translation table entry | Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Charles F. Webb | 2013-12-31 |
| 8516195 | Extract cache attribute facility and instruction therefore | Dan F. Greiner | 2013-08-20 |
| 8489853 | Executing a perform frame management instruction | Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Gustav E. Sittmann, III | 2013-07-16 |
| 8452942 | Invalidating a range of two or more translation table entries and instruction therefore | Lisa C. Heller, Erwin Pfeffer, Kenneth E. Plambeck | 2013-05-28 |