Issued Patents All Time
Showing 51–75 of 183 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7203608 | Impedane measurement of chip, package, and board power supply system using pseudo impulse response | Makoto Aikawa, Brian Flachs, Paul M. Harvey, Brad W. Michael, Yaping Zhou | 2007-04-10 |
| 7170328 | Scannable latch | Joel A. Silberman, Osamu Takahashi | 2007-01-30 |
| 7170316 | Programmable logic array latch | Brian Flachs, Joel A. Silberman, Osamu Takahashi | 2007-01-30 |
| 7165006 | Scan chain disable function for power saving | Joel A. Silberman, Osamu Takahashi, James D. Warnock, Dieter Wendel | 2007-01-16 |
| 7149877 | Byte execution unit for carrying out byte instructions in a processor | Hwa-Joon Oh, Brad W. Michael, Silvia M. Mueller, Kevin D. Tran | 2006-12-12 |
| 7139215 | Apparatus and method of word line decoding for deep pipelined memory | Toru Asano, Takaaki Nakazato, Osamu Takahashi | 2006-11-21 |
| 7137021 | Power saving in FPU with gated power based on opcodes and data | Silvia M. Mueller, Hwa-Joon Oh | 2006-11-14 |
| 7113443 | Method of address distribution time reduction for high speed memory macro | Hiroaki Murakami, Shohji Onishi, Osamu Takahashi | 2006-09-26 |
| 7058830 | Power saving in a floating point unit using a multiplier and aligner bypass | Silvia M. Mueller, Hwa-Joon Oh, Kevin D. Tran | 2006-06-06 |
| 7053668 | SOI sense amplifier with cross-coupled body terminal | Takaaki Nakazato, Toru Asano, Osamu Takahashi | 2006-05-30 |
| 7046045 | SOI sense amplifier with cross-coupled bit line structure | Takaaki Nakazato, Toru Asano, Osamu Takahashi | 2006-05-16 |
| 7043579 | Ring-topology based multiprocessor data access bus | Harm Peter Hofstee, John Liberty, Peichun Peter Liu | 2006-05-09 |
| 6983387 | Microprocessor chip simultaneous switching current reduction method and apparatus | David William Boerstler, Harm Peter Hofstee, Peichun Peter Liu | 2006-01-03 |
| 6982954 | Communications bus with redundant signal paths and method for compensating for signal path errors in a communications bus | Harm Peter Hofstee | 2006-01-03 |
| 6944088 | Apparatus and method for generating memory access signals, and memory accessed using said signals | Toru Asano, Joel A. Silberman, Osamu Takahashi | 2005-09-13 |
| 6941335 | Random carry-in for floating-point operations | Harm Peter Hofstee, Kevin John Nowka, Steven Douglas Posluszny, Joel A. Silberman | 2005-09-06 |
| 6927615 | Low skew, power efficient local clock signal generation system | Joel A. Silberman, Osamu Takahashi, James D. Warnock, Dieter Wendel | 2005-08-09 |
| 6915506 | Method and apparatus for evaluating results of multiple software tools | Sam Dinkin, Harm Peter Hofstee, Stephen Douglas Posluszny | 2005-07-05 |
| 6914453 | Integrated logic and latch design with clock gating at static input signals | Hwa-Joon Oh, Joel A. Silberman, Naoka Yano | 2005-07-05 |
| 6910165 | Digital random noise generator | Howard H. Chen, Li-Kong Wang, Louis L. Hsu, Tin-Chee Lo | 2005-06-21 |
| 6898135 | Latch type sense amplifier method and apparatus | Toru Asano, Takaaki Nakazato, Osamu Takahashi | 2005-05-24 |
| 6885596 | Apparatus and method of wordline/bitline redundancy control using shift registers in an SRAM | Toru Asano, Takaaki Nakazato, Osamu Takahashi | 2005-04-26 |
| 6850456 | Subarray control and subarray cell access in a memory module | Toru Asano, Takaaki Nakazato, Osamu Takahashi | 2005-02-01 |
| 6833736 | Pulse generating circuit | Takaaki Nakazato, Toru Asano, Osamu Takahashi, Atsushi Kawasumi | 2004-12-21 |
| 6829682 | Destructive read architecture for dynamic random access memories | Toshiaki Kirihata, Hwa-Joon Oh, Matthew R. Wordeman | 2004-12-07 |