Issued Patents All Time
Showing 76–100 of 183 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6825695 | Unified local clock buffer structures | Joel A. Silberman, Osamu Takahashi, James D. Warnock, Dieter Wendel | 2004-11-30 |
| 6826110 | Cell circuit for multiport memory using decoder | Harm Peter Hofstee, Shoji Onishi, Osamu Takahashi | 2004-11-30 |
| 6772368 | Multiprocessor with pair-wise high reliability mode, and method therefore | Harm Peter Hofstee, Ravi Nair, Steven Douglas Posluszny | 2004-08-03 |
| 6760819 | Symmetric multiprocessor coherence mechanism | Harm Peter Hofstee, Charles Ray Johns, John Liberty, Thuong Quang Truong | 2004-07-06 |
| 6744282 | Latching dynamic logic structure, and integrated circuit including same | Joel A. Silberman, Osamu Takahashi, James D. Warnock, Dieter Wendel | 2004-06-01 |
| 6717882 | Cell circuit for multiport memory using 3-way multiplexer | Harm Peter Hofstee, Shoji Onishi, Osamu Takahashi | 2004-04-06 |
| 6600959 | Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays | Paula Kristine Coulman, Brian Flachs, Harm Peter Hofstee, Jaehong Park, Stephen Douglas Posluszny +2 more | 2003-07-29 |
| 6594679 | Leading-zero anticipator having an independent sign bit determination module | Kyung Tek Lee, Kevin John Nowka | 2003-07-15 |
| 6587388 | Method and apparatus for reducing write operation time in dynamic random access memories | Toshiaki Kirihata, Hwa-Joon Oh | 2003-07-01 |
| 6584485 | 4 to 2 adder | Naoaki Aoki, Nobuo Kojima, Ohsang Kwon | 2003-06-24 |
| 6574698 | Method and system for accessing a cache memory within a data processing system | Joel A. Silberman | 2003-06-03 |
| 6535041 | Strobe circuit keeper arrangement providing reduced power consumption | Robert J. Bucki, Jeffrey Herbert Fischer, Joel A. Silberman, Osamu Takahashi | 2003-03-18 |
| 6519174 | Early write DRAM architecture with vertically folded bitlines | Toshiaki Kirihata | 2003-02-11 |
| 6510093 | Method and apparatus for cycle time reduction in a memory system using alternating reference cells and isolated sense lines | Hwa-Joon Oh | 2003-01-21 |
| 6502224 | Method and apparatus for synthesizing levelized logic | Harm Peter Hofstee, Stephen Douglas Posluszny, Joel A. Silberman, Osamu Takahashi, Dieter Wendel | 2002-12-31 |
| 6453390 | Processor cycle time independent pipeline cache and method for pipelining data from a cache | Naoaki Aoki, Nobuo Kojima, Joel A. Silberman | 2002-09-17 |
| 6453258 | Optimized burn-in for fixed time dynamic logic circuitry | Naoaki Aoki, Joel A. Silberman, Osamu Takahashi | 2002-09-17 |
| 6430672 | Method for performing address mapping using two lookup tables | Harm Peter Hofstee, Osamu Takahashi, Jan Van Lunteren | 2002-08-06 |
| 6421699 | Method and system for a speedup of a bit multiplier | Perng Shyong Lin, Joel A. Silberman | 2002-07-16 |
| 6404689 | Method and structure for hiding a refresh operation in a DRAM having an interlocked pipeline | Toshiaki Kirihata, Chorng-Lii Hwang | 2002-06-11 |
| 6393446 | 32-bit and 64-bit dual mode rotator | Hung C. Ngo, Jaehong Park, Joel A. Silberman | 2002-05-21 |
| 6360238 | Leading zero/one anticipator having an integrated sign selector | Kyung Tek Lee, Hung C. Ngo, Kevin John Nowka | 2002-03-19 |
| 6356990 | Set-associative cache memory having a built-in set prediction array | Naoaki Aoki, Nobuo Kojima, Joel A. Silberman | 2002-03-12 |
| 6345286 | 6-to-3 carry-save adder | Hung C. Ngo, Kevin John Nowka | 2002-02-05 |
| 6334184 | Processor and method of fetching an instruction that select one of a plurality of decoded fetch addresses generated in parallel to form a memory request | Joel A. Silberman | 2001-12-25 |