Issued Patents All Time
Showing 126–150 of 183 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6038659 | Method for using read-only memory to generate controls for microprocessor | Harm Peter Hofstee, David Meltzer, Joel A. Silberman | 2000-03-14 |
| 6035390 | Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical operation | Jeffrey L. Burns, Kevin John Nowka, Joel A. Silberman | 2000-03-07 |
| 6021461 | Method for reducing power consumption in a set associative cache memory system | Philip G. Emma, William Robert Reohr, Joel A. Silberman | 2000-02-01 |
| 6014763 | At-speed scan testing | Harm Peter Hofstee, Kevin John Nowka, Joel A. Silberman | 2000-01-11 |
| 6003119 | Memory circuit for reordering selected data in parallel with selection of the data from the memory circuit | Joel A. Silberman | 1999-12-14 |
| 5964827 | High-speed binary adder | Hung C. Ngo, Joel A. Silberman | 1999-10-12 |
| 5926487 | High performance registers for pulsed logic | Terry I. Chappell, Michael Kevin Ciraula, Max Eduardo De Ycaza, Rudolf A. Haring, Talal K. Jaber +3 more | 1999-07-20 |
| 5911153 | Memory design which facilitates incremental fetch and store requests off applied base address requests | Philip G. Emma, William Robert Reohr, Joel A. Silberman | 1999-06-08 |
| 5881274 | Method and apparatus for performing add and rotate as a single instruction within a processor | Hung C. Ngo, Joel A. Silberman | 1999-03-09 |
| 5877972 | High speed incrementer with array method | Naoaki Aoki, Osamu Takahashi, Joel A. Silberman | 1999-03-02 |
| 5812838 | Branch history table | Perng Shyong Lin, Joel A. Silberman | 1998-09-22 |
| 5777918 | Fast multiple operands adder/subtracter based on shifting | Kin Shing Chan, Chiao-Mei Chuang, Alessandro Marchioro | 1998-07-07 |
| 5771268 | High speed rotator with array method | Naoaki Aoki, Osamu Takahashi, Joel A. Silberman | 1998-06-23 |
| 5710731 | Combined adder and decoder digital circuit | Michael Kevin Ciraula, Joel A. Silberman | 1998-01-20 |
| 5635858 | Zero-stopping incrementers | Chin-An Chang | 1997-06-03 |
| 5621696 | Virtual multiple-read port memory array | Joseph J. Nocera, Jr. | 1997-04-15 |
| 5541887 | Multiple port cells with improved testability | Wei Hwang, Toshiaki Kirihata | 1996-07-30 |
| 5483179 | Data output drivers with pull-up devices | Toshiaki Kirihata, Matthew R. Wordeman | 1996-01-09 |
| 5453953 | Bandgap voltage reference generator | Hyun Jong Shin, Wei Hwang | 1995-09-26 |
| 5451535 | Method for manufacturing a memory cell | Kevin K. Chan, Dieter Kern, Young Hoon Lee | 1995-09-19 |
| 5418477 | Data output buffer pull-down circuit for TTL interface | Hyun Jong Shin | 1995-05-23 |
| 5362663 | Method of forming double well substrate plate trench DRAM cell array | Gary B. Bronner, Wei Hwang | 1994-11-08 |
| 5359552 | Power supply tracking regulator for a memory array | Hyun Jong Shin, Wei Hwang | 1994-10-25 |
| 5343092 | Self-biased feedback-controlled active pull-down signal switching | Hyun Jong Shin | 1994-08-30 |
| 5339274 | Variable bitline precharge voltage sensing technique for DRAM structures | Toshiaki Kirihata, Hyun Jong Shin, Toshio Sunaga, Yoichi Taira, Lewis M. Terman | 1994-08-16 |