Issued Patents All Time
Showing 151–175 of 183 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5336629 | Folder Bitline DRAM having access transistors stacked above trench storage capacitors, each such transistor employing a planar semiconductor body which spans adjacent capacitors | Wei Hwang, Lewis M. Terman, Matthew R. Wordeman | 1994-08-09 |
| 5331189 | Asymmetric multilayered dielectric material and a flash EEPROM using the same | Kevin K. Chan, Dieter Kern, Young Hoon Lee | 1994-07-19 |
| 5321647 | Semiconductor memory device and operational method with reduced well noise | Gary B. Bronner | 1994-06-14 |
| 5300800 | Low leakage substrate plate DRAM cell | Gary B. Bronner, Wei Hwang | 1994-04-05 |
| 5292678 | Forming a bit line configuration for semiconductor memory | Wei Hwang | 1994-03-08 |
| 5289432 | Dual-port static random access memory cell | Hyun Jong Shin | 1994-02-22 |
| 5280452 | Power saving semsing circuits for dynamic random access memory | Lewis M. Terman | 1994-01-18 |
| 5268871 | Power supply tracking regulator for a memory array | Hyun Jong Shin, Wei Hwang | 1993-12-07 |
| 5257232 | Sensing circuit for semiconductor memory with limited bitline voltage swing | Koji Kitamura, Toshiaki Kirihata, Toshio Sunaga | 1993-10-26 |
| 5253202 | Word line driver circuit for dynamic random access memories | Gary B. Bronner, Wei Hwang | 1993-10-12 |
| 5250829 | Double well substrate plate trench DRAM cell array | Gary B. Bronner, Wei Hwang | 1993-10-05 |
| 5214603 | Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors | Wei Hwang, Lewis M. Terman, Matthew R. Wordeman | 1993-05-25 |
| 5212616 | Voltage regulation and latch-up protection circuits | Robert L. Franch | 1993-05-18 |
| 5204280 | Process for fabricating multiple pillars inside a dram trench for increased capacitor surface | John C. Malinowski | 1993-04-20 |
| 5185719 | High speed dynamic, random access memory with extended reset/precharge time | Wei Hwang | 1993-02-09 |
| 5170243 | Bit line configuration for semiconductor memory | Wei Hwang | 1992-12-08 |
| 5162668 | Small dropout on-chip voltage regulators with boosted power supply | Chih-Liang Chen, Hyun Jong Shin | 1992-11-10 |
| 5157634 | DRAM having extended refresh time | Robert L. Franch, Wei Hwang | 1992-10-20 |
| 5144165 | CMOS off-chip driver circuits | Wei Hwang, Hyun Jong Shin | 1992-09-01 |
| 5107459 | Stacked bit-line architecture for high density cross-point memory cell array | Christopher Chu, Wei Hwang, Nicky C. Lu | 1992-04-21 |
| 5075571 | PMOS wordline boost cricuit for DRAM | Wei Hwang, Yoichi Taira | 1991-12-24 |
| 5034787 | Structure and fabrication method for a double trench memory cell device | Wei Hwang | 1991-07-23 |
| 5021355 | Method of fabricating cross-point lightly-doped drain-source trench transistor | Wei Hwang, Nicky C. Lu | 1991-06-04 |
| 4999518 | MOS switching circuit having gate enhanced lateral bipolar transistor | Chih-Liang Chen, Hyun Jong Shin | 1991-03-12 |
| 4988637 | Method for fabricating a mesa transistor-trench capacitor memory cell structure | Wei Hwang | 1991-01-29 |