Issued Patents All Time
Showing 101–125 of 183 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6294929 | Balanced-delay programmable logic array and method for balancing programmable logic array delays | Paula Kristine Coulman, Jaehong Park, Stephen Douglas Posluszny, Osamu Takahashi | 2001-09-25 |
| 6285218 | Method and apparatus for implementing logic using mask-programmable dynamic logic gates | Hung C. Ngo, Jaehong Park, Osamu Takahashi | 2001-09-04 |
| 6282557 | Low latency fused multiply-adder | Hung C. Ngo, Kevin John Nowka | 2001-08-28 |
| 6279024 | High performance, low power incrementer for dynamic circuits | Barbara A. Chappell, Terry I. Chappell, Mark S. Milshtein | 2001-08-21 |
| 6268660 | Silicon packaging with through wafer interconnects | Harm Peter Hofstee, Michael J. Shapiro | 2001-07-31 |
| 6239620 | Method and apparatus for generating true/complement signals | Naoaki Aoki, Nobuo Kojima, Joel A. Silberman | 2001-05-29 |
| 6237085 | Processor and method for generating less than (LT), Greater than (GT), and equal to (EQ) condition code bits concurrent with a logical or complex operation | Jeffrey L. Burns, Kevin John Nowka | 2001-05-22 |
| 6232798 | Self-resetting circuit timing correction | Paula Kristine Coulman, Joel A. Silberman, Osamu Takahashi | 2001-05-15 |
| 6232872 | Comparator | Hung C. Ngo, Jaehong Park | 2001-05-15 |
| 6229338 | Method and apparatus for reducing dynamic programmable logic array propagation delay | Paula Kristine Coulman, Joel A. Silberman, Osamu Takahashi | 2001-05-08 |
| 6226731 | Method and system for accessing a cache memory within a data-processing system utilizing a pre-calculated comparison array | Joel A. Silberman | 2001-05-01 |
| 6221769 | Method for integrated circuit power and electrical connections via through-wafer interconnects | Kevin John Nowka, Michael J. Shapiro | 2001-04-24 |
| 6212619 | System and method for high-speed register renaming by counting | Harm Peter Hofstee, Kevin John Nowka, Joel A. Silberman | 2001-04-03 |
| 6178437 | Method and apparatus for anticipating leading digits and normalization shift amounts in a floating-point processor | Hung C. Ngo, Kevin John Nowka | 2001-01-23 |
| 6175535 | Cycle control circuit for extending a cycle period of a dynamic memory device subarray | Manabu Ohkubo, Shohji Onishi, Osamu Takahashi | 2001-01-16 |
| 6175852 | High-speed binary adder | Hung C. Ngo, Kevin John Nowka | 2001-01-16 |
| 6172920 | Data transfer using two-stage bit switch in memory circuit | Manabu Ohkubo, Shohji Onishi, Osamu Takahashi | 2001-01-09 |
| 6166437 | Silicon on silicon package with precision align macro | Kevin John Nowka, Michael J. Shapiro | 2000-12-26 |
| 6161164 | Content addressable memory accessed by the sum of two operands | Joel A. Silberman | 2000-12-12 |
| 6138208 | Multiple level cache memory with overlapped L1 and L2 memory access | Harm Peter Hofstee, David Meltzer, Joel A. Silberman | 2000-10-24 |
| 6104213 | Domino logic circuit having a clocked precharge | Uttam Shyamalindu Ghoshal, Joel A. Silberman, Osamu Takahashi | 2000-08-15 |
| 6088763 | Method and apparatus for translating an effective address to a real address within a cache memory | Joel A. Silberman | 2000-07-11 |
| 6076140 | Set associative cache memory system with reduced power consumption | Philip G. Emma, William Robert Reohr, Joel A. Silberman | 2000-06-13 |
| 6065028 | Multifunctional macro | Joel A. Silberman | 2000-05-16 |
| 6060759 | Method and apparatus for creating improved inductors for use with electronic oscillators | Uttam S. Ghoshal, Kyung Tek Lee | 2000-05-09 |