Issued Patents All Time
Showing 776–800 of 836 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8030649 | Scan testing in single-chip multicore systems | — | 2011-10-04 |
| 8010953 | Method for compiling scalar code for a single instruction multiple data (SIMD) execution engine | — | 2011-08-30 |
| 8006070 | Method and apparatus for inhibiting fetch throttling when a processor encounters a low confidence branch instruction in an information handling system | Robert Alan Philhower, Raymond Cheung Yeung | 2011-08-23 |
| 7987464 | Logical partitioning and virtualization in a heterogeneous architecture | Michael Norman Day, Mark Richard Nutter, James Xenidis | 2011-07-26 |
| 7977965 | Soft error detection for latches | Bruce M. Fleischer | 2011-07-12 |
| 7925853 | Method and apparatus for controlling memory array gating when a processor executes a low confidence branch instruction in an information handling system | Robert Alan Philhower, Raymond Cheung Yeung | 2011-04-12 |
| 7900025 | Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations | — | 2011-03-01 |
| 7877759 | System for efficient performance monitoring of a large number of simultaneous events | Alan Gara, Valentina Salapura | 2011-01-25 |
| 7877582 | Multi-addressable register file | Brett Olsson | 2011-01-25 |
| 7865693 | Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type | Alexandre E. Eichenberger, Bruce M. Fleischer | 2011-01-04 |
| 7865699 | Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code | Erik R. Altman, David Arnold Luick, Daniel A. Prener, Jude A. Rivers, Sumedh W. Sathaye +1 more | 2011-01-04 |
| 7849293 | Method and structure for low latency load-tagged pointer instruction for computer microarchitechture | Bartholomew Blaner | 2010-12-07 |
| 7849241 | Memory compression method and apparatus for heterogeneous processor architectures in an information handling system | Barry L. Minor | 2010-12-07 |
| 7849294 | Sharing data in internal and memory representations with dynamic data-driven conversion | Brett Olsson | 2010-12-07 |
| 7840954 | Compilation for a SIMD RISC processor | — | 2010-11-23 |
| 7836260 | Low complexity speculative multithreading system based on unmodified microprocessor core | Alan Gara, Valentina Salapura | 2010-11-16 |
| 7797521 | Method, system, and computer program product for path-correlated indirect address predictions | Richard J. Eickemeyer, Ravi Nair, Robert Alan Philhower | 2010-09-14 |
| 7793081 | Implementing instruction set architectures with non-contiguous register file specifiers | Robert K. Montoye, Brett Olsson, John-David Wellman | 2010-09-07 |
| 7752505 | Method and apparatus for detection of data errors in tag arrays | Michael M. Tsao | 2010-07-06 |
| 7735072 | Method and apparatus for profiling computer program execution | Erik R. Altman, Kemal Ebcioglu, Sumedh W. Sathaye | 2010-06-08 |
| 7725659 | Alignment of cache fetch return data relative to a thread | Hans M. Jacobson, Robert Alan Philhower | 2010-05-25 |
| 7725682 | Method and apparatus for sharing storage and execution resources between architectural units in a microprocessor using a polymorphic function unit | Balaram Sinharoy | 2010-05-25 |
| 7627742 | Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system | Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Ravi Nair, Robert Alan Philhower +2 more | 2009-12-01 |
| 7620756 | Method and apparatus for updating wide storage array over a narrow bus | Alan Gara, Valentina Salapura | 2009-11-17 |
| 7523298 | Polymorphic branch predictor and method with selectable mode of prediction | — | 2009-04-21 |