Issued Patents All Time
Showing 801–825 of 836 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7523379 | Method for time-delayed data protection | — | 2009-04-21 |
| 7512772 | Soft error handling in microprocessors | Robert Alan Philhower | 2009-03-31 |
| 7512745 | Method for garbage collection in heterogeneous multiprocessor systems | John Kevin Patrick O'Brien, Kathryn M. O'Brien | 2009-03-31 |
| 7509457 | Non-homogeneous multi-processor system with shared memory | Erik R. Altman, Peter G. Capek, Charles Ray Johns, Harm Peter Hofstee, Martin E. Hopkins +4 more | 2009-03-24 |
| 7496673 | SIMD-RISC microprocessor architecture | Harm Peter Hofstee, Martin E. Hopkins, James Allan Kahle | 2009-02-24 |
| 7496733 | System and method of execution of register pointer instructions ahead of instruction issues | Erik R. Altman, Jude A. Rivers, Sumedh W. Sathaye, John-David Wellman, Victor Zyuban | 2009-02-24 |
| 7487330 | Method and apparatus for transferring control in a computer system with dynamic compilation capability | Erik R. Altman, Kemal Ebcioglu, David Arnold Luick | 2009-02-03 |
| 7475224 | Register map unit supporting mapping of multiple register specifier classes | — | 2009-01-06 |
| 7461209 | Transient cache storage with discard function for disposable data | Erik R. Altman, Robert K. Montoye, Jude A. Rivers, Sumedh W. Sathaye, John-David Wellman +1 more | 2008-12-02 |
| 7461383 | Method and apparatus for efficient performance monitoring of a large number of simultaneous events | Alan Gara, Valentina Salapura | 2008-12-02 |
| 7421566 | Implementing instruction set architectures with non-contiguous register file specifiers | Robert K. Montoye, Brett Olsson, John-David Wellman | 2008-09-02 |
| 7404041 | Low complexity speculative multithreading system based on unmodified microprocessor core | Alan Gara, Valentina Salapura | 2008-07-22 |
| 7363432 | Method and apparatus for directory-based coherence with distributed directory management | Charles Ray Johns, Thoung Quang Truong | 2008-04-22 |
| 7340588 | Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code | Erik R. Altman, David Arnold Luick, Daniel A. Prener, Jude A. Rivers, Sumedh W. Sathaye +1 more | 2008-03-04 |
| 7325124 | System and method of execution of register pointer instructions ahead of instruction issue | Erik R. Altman, Jude A. Rivers, Sumedh W. Sathaye, John-David Wellman, Victor Zyuban | 2008-01-29 |
| 7321956 | Method and apparatus for directory-based coherence with distributed directory management utilizing prefetch caches | Charles Ray Johns, Thoung Quang Truong | 2008-01-22 |
| 7243333 | Method and apparatus for creating and executing integrated executables in a heterogeneous architecture | Kathryn M. O'Brien, John Kevin Patrick O'Brien, Valentina Salapura | 2007-07-10 |
| 7225431 | Method and apparatus for setting breakpoints when debugging integrated executables in a heterogeneous architecture | Kathryn M. O'Brien, John Kevin Patrick O'Brien, Valentina Salapura | 2007-05-29 |
| 7222332 | Method and apparatus for overlay management within an integrated executable for a heterogeneous architecture | Kathryn M. O'Brien, John Kevin Patrick O'Brien, Valentina Salapura | 2007-05-22 |
| 7213123 | Method and apparatus for mapping debugging information when debugging integrated executables in a heterogeneous architecture | Kathryn M. O'Brien, John Kevin Patrick O'Brien, Valentina Salapura | 2007-05-01 |
| 7200840 | Method and apparatus for enabling access to global data by a plurality of codes in an integrated executable for a heterogeneous architecture | Kathryn M. O'Brien, John Kevin Patrick O'Brien, Valentina Salapura | 2007-04-03 |
| 7134028 | Processor with low overhead predictive supply voltage gating for leakage power reduction | Pradip Bose, David M. Brooks, Peter W. Cook, Philip G. Emma, Stanley E. Schuster +1 more | 2006-11-07 |
| 7085914 | Methods for renaming stack references to processor registers | — | 2006-08-01 |
| 7051168 | Method and apparatus for aligning memory write data in a microprocessor | Martin E. Hopkins, H. Peter Hofstee | 2006-05-23 |
| 7051255 | Method and apparatus for reducing power dissipation in latches during scan operation | — | 2006-05-23 |