Issued Patents All Time
Showing 726–750 of 836 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9021511 | Runtime management of TOC pointer save and restore commands | — | 2015-04-28 |
| 8984042 | Mixed precision estimate instruction computing narrow precision result for wide precision inputs | Valentina Salapura | 2015-03-17 |
| 8972788 | Ticket consolidation | Ruchi Mahindru, Valentina Salapura | 2015-03-03 |
| 8930752 | Scheduler for multiprocessor system switch with selective pairing | Alan Gara, Valentina Salapura | 2015-01-06 |
| 8918623 | Implementing instruction set architectures with non-contiguous register file specifiers | Robert K. Montoye, Brett Olsson, John-David Wellman | 2014-12-23 |
| 8904153 | Vector loads with multiple vector elements from a same cache line in a scattered load operation | Alexandre E. Eichenberger, Valentina Salapura | 2014-12-02 |
| 8904151 | Method and apparatus for the dynamic identification and merging of instructions for execution on a wide datapath | Balaram Sinharoy | 2014-12-02 |
| 8893079 | Methods for generating code for an architecture encoding an extended register specification | Robert K. Montoye, Brett Olsson, John-David Wellman | 2014-11-18 |
| 8893095 | Methods for generating code for an architecture encoding an extended register specification | Robert K. Montoye, Brett Olsson, John-David Wellman | 2014-11-18 |
| 8832669 | Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization | Robert J. Blainey, James L. McInnes, Steven J. Munroe | 2014-09-09 |
| 8812824 | Method and apparatus for employing multi-bit register file cells and SMT thread groups | — | 2014-08-19 |
| 8756591 | Generating compiled code that indicates register liveness | Valentina Salapura | 2014-06-17 |
| 8738859 | Hybrid caching techniques and garbage collection using hybrid caching techniques | Chen-Yong Cher | 2014-05-27 |
| 8713547 | Generating compiled code that indicates register liveness | Valentina Salapura | 2014-04-29 |
| 8695010 | Privilege level aware processor hardware resource management facility | Giles R. Frazier, Naresh Nayar | 2014-04-08 |
| 8671311 | Multiprocessor switch with selective pairing | Alan Gara, Valentina Salapura | 2014-03-11 |
| 8650240 | Complex matrix multiplication operations with data pre-conditioning in a high performance computing architecture | Alexandre E. Eichenberger, John A. Gunnels | 2014-02-11 |
| 8635492 | State recovery and lockstep execution restart in a system with multiprocessor pairing | Alan Gara, Valentina Salapura | 2014-01-21 |
| 8615745 | Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization | Robert J. Blainey, James L. McInnes, Steven J. Munroe | 2013-12-24 |
| 8615746 | Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization | Robert J. Blainey, James L. McInnes, Steven J. Munroe | 2013-12-24 |
| 8612959 | Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization | Robert J. Blainey, James L. McInnes, Michael R. Meissner, Steven J. Munroe | 2013-12-17 |
| 8607211 | Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization | Robert J. Blainey, James L. McInnes, Michael R. Meissner, Steven J. Munroe | 2013-12-10 |
| 8589662 | Accepting or rolling back execution of instructions based on comparing predicted and actual dependency control signals | Erik R. Altman, Jude A. Rivers, Sumedh W. Sathaye, John-David Wellman, Victor Zyuban | 2013-11-19 |
| 8577950 | Matrix multiplication operations with data pre-conditioning in a high performance computing architecture | Alexandre E. Eichenberger, John A. Gunnels | 2013-11-05 |
| 8572586 | Optimized scalar promotion with load and splat SIMD instructions | Alexandre E. Eichenberger, John A. Gunnels | 2013-10-29 |