Issued Patents All Time
Showing 51–75 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9378318 | Shared channel masks in on-product test compression system | Steven M. Douskey | 2016-06-28 |
| 9372232 | Collecting diagnostic data from chips | Steven M. Douskey, Ryan A. Fitch, William V. Huott | 2016-06-21 |
| 9355203 | Shared channel masks in on-product test compression system | Steven M. Douskey | 2016-05-31 |
| 9297856 | Implementing MISR compression methods for test time reduction | Steven M. Douskey, Cedric Lichtenau | 2016-03-29 |
| 9292398 | Design-based weighting for logic built-in self-test | Gregory J. Cook, Timothy J. Koprowski, Cedric Lichtenau | 2016-03-22 |
| 9292399 | Design-Based weighting for logic built-in self-test | Gregory J. Cook, Timothy J. Koprowski, Cedric Lichtenau | 2016-03-22 |
| 9285423 | Managing chip testing data | Steven M. Douskey, Ryan A. Fitch, William V. Huott | 2016-03-15 |
| 9268892 | Identification of unknown sources for logic built-in self test in verification | Satya R. S. Bhamidipati, Cedric Lichtenau, Srinivas V. N. Polisetty | 2016-02-23 |
| 9151800 | Chip testing with exclusive OR | Steven M. Douskey, Cedric Lichtenau | 2015-10-06 |
| 9134373 | Hierarchal test block test pattern reduction in on-product test compression system | Steven M. Douskey | 2015-09-15 |
| 9134375 | Hierarchal test block test pattern reduction in on-product test compression system | Steven M. Douskey | 2015-09-15 |
| 9110135 | Chip testing with exclusive OR | Steven M. Douskey, Cedric Lichtenau | 2015-08-18 |
| 8768985 | Automated file relocation | Frank Eliot Levine, Stella Lee Taylor, Anna W. Topol | 2014-07-01 |
| 8566059 | Insertion of faults in logic model used in simulation | Rao H. Desineni, Maroun Kassab, Leah Pastel | 2013-10-22 |
| 8255928 | Automated termination of selected software applications in response system events | Frank Eliot Levine, Stella Lee Taylor, Anna W. Topol | 2012-08-28 |
| 8176105 | Automated file relocation | Frank Eliot Levine, Stella Lee Taylor, Anna W. Topol | 2012-05-08 |
| 8095837 | Method and apparatus for improving random pattern testing of logic structures | Barry W. Krumm, Patrick J. Meaney, Bryan J. Robbins | 2012-01-10 |
| 7882454 | Apparatus and method for improved test controllability and observability of random resistant logic | Haoxing Ren, Ronald Gene Walther, Rona Yaari | 2011-02-01 |
| 7831863 | Method for enhancing the diagnostic accuracy of a VLSI chip | Gary W. Maier, Franco Motika, Phong T. Tran | 2010-11-09 |
| 6836865 | Method and apparatus for facilitating random pattern testing of logic structures | William V. Huott, Bryan J. Robbins, Timothy Charest | 2004-12-28 |
| 6728914 | Random path delay testing methodology | Kevin William McCauley, William V. Huott, Peilin Song, Richard F. Rizzolo, Ulrich Baur +1 more | 2004-04-27 |
| 6671838 | Method and apparatus for programmable LBIST channel weighting | Timothy J. Koprowski, Lawrence K. Lange, Bryan J. Robbins | 2003-12-30 |
| 6442720 | Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysis | Timothy J. Koprowski, Richard F. Rizzolo, Peilin Song | 2002-08-27 |
| 6314540 | Partitioned pseudo-random logic test for improved manufacturability of semiconductor chips | William V. Huott, Gregory O'Malley, Bryan J. Robbins | 2001-11-06 |
| 6308290 | Look ahead scan chain diagnostic method | Orazio P. Forlenza, Franco Motika | 2001-10-23 |