Issued Patents All Time
Showing 26–50 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10254336 | Iterative N-detect based logic diagnostic technique | Gary W. Maier, Franco Motika, Phong T. Tran | 2019-04-09 |
| 10247776 | Structurally assisted functional test and diagnostics for integrated circuits | Franco Motika, Gerard M. Salem | 2019-04-02 |
| 10168386 | Scan chain latency reduction | George Antony, Sridhar H. Rangarajan, Shrinivas Shenoy | 2019-01-01 |
| 10169510 | Dynamic fault model generation for diagnostics simulation and pattern generation | Gary W. Maier, Franco Motika, Phong T. Tran | 2019-01-01 |
| 10107860 | Bitwise rotating scan section for microelectronic chip testing and diagnostics | Todd L. Cohen, Hari Krishnan Rajeev, Timothy C. Taylor | 2018-10-23 |
| 10088524 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Raghu G. GopalaKrishnaSetty, Cedric Lichtenau | 2018-10-02 |
| 10067183 | Portion isolation architecture for chip isolation test | Steven M. Douskey, Raghu G. Gaurav, Hari Krishnan Rajeev | 2018-09-04 |
| 10060971 | Adjusting latency in a scan cell | Steven M. Douskey, Raghu G. GopalaKrishnaSetty | 2018-08-28 |
| 10024910 | Iterative N-detect based logic diagnostic technique | Gary W. Maier, Franco Motika, Phong T. Tran | 2018-07-17 |
| 10018671 | Reducing power requirements and switching during logic built-in-self-test and scan test | Satya R. S. Bhamidipati, Cedric Lichtenau | 2018-07-10 |
| 10018672 | Reducing power requirements and switching during logic built-in-self-test and scan test | Satya R. S. Bhamidipati, Cedric Lichtenau | 2018-07-10 |
| 10001523 | Adjusting latency in a scan cell | Steven M. Douskey, Raghu G. GopalaKrishnaSetty | 2018-06-19 |
| 9929749 | Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry | Michael Fee, Ronald J. Frishmuth, Cedric Lichtenau | 2018-03-27 |
| 9923579 | Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry | Michael Fee, Ronald J. Frishmuth, Cedric Lichtenau | 2018-03-20 |
| 9915701 | Bypassing an encoded latch on a chip during a test-pattern scan | Michael Fee, Ronald J. Frishmuth, Cedric Lichtenau | 2018-03-13 |
| 9910090 | Bypassing an encoded latch on a chip during a test-pattern scan | Michael Fee, Ronald J. Frishmuth, Cedric Lichtenau | 2018-03-06 |
| 9852245 | Dynamic fault model generation for diagnostics simulation and pattern generation | Gary W. Maier, Franco Motika, Phong T. Tran | 2017-12-26 |
| 9746516 | Collecting diagnostic data from chips | Steven M. Douskey, Ryan A. Fitch, William V. Huott | 2017-08-29 |
| 9689920 | Identification of unknown sources for logic built-in self test in verification | Satya R. S. Bhamidipati, Cedric Lichtenau, Srinivas V. N. Polisetty | 2017-06-27 |
| 9651623 | Reducing power requirements and switching during logic built-in-self-test and scan test | Satya R. S. Bhamidipati, Cedric Lichtenau | 2017-05-16 |
| 9651616 | Reducing power requirements and switching during logic built-in-self-test and scan test | Satya R. S. Bhamidipati, Cedric Lichtenau | 2017-05-16 |
| 9588177 | Optimizing generation of test configurations for built-in self-testing | Eugene Atwood, Paul Jacob Logsdon, Franco Motika, Andrew A. Turner | 2017-03-07 |
| 9557381 | Physically aware insertion of diagnostic circuit elements | William V. Huott, Sridhar H. Rangarajan, Robert C. Redburn, Andrew A. Turner | 2017-01-31 |
| 9552449 | Dynamic fault model generation for diagnostics simulation and pattern generation | Gary W. Maier, Franco Motika, Phong T. Tran | 2017-01-24 |
| 9404969 | Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad dies | Brion Keller, Steven M. Douskey | 2016-08-02 |