Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10191112 | Early development of a database of fail signatures for systematic defects in integrated circuit (IC) chips | Atul Chittora, Yan Pan, Sherwin Fernandes, Thomas Herrmann | 2019-01-29 |
| 8566059 | Insertion of faults in logic model used in simulation | Maroun Kassab, Mary P. Kusko, Leah Pastel | 2013-10-22 |
| 8136082 | Method for testing integrated circuits | Maroun Kassab, Franco Motika, Leah Pastel | 2012-03-13 |
| 7971176 | Method for testing integrated circuits | Maroun Kassab, Franco Motika, Leah Pastel | 2011-06-28 |
| 7870519 | Method for determining features associated with fails of integrated circuits | Maroun Kassab, Leah Pfeifer Pastel | 2011-01-11 |
| 7853848 | System and method for signature-based systematic condition detection and analysis | Maroun Kassab, Leah Pastel | 2010-12-14 |
| 7770080 | Using neighborhood functions to extract logical models of physical failures using layout based diagnosis | Ronald DeShawn Blanton, Wojciech P. Maly | 2010-08-03 |
| 7682842 | Method of adaptively selecting chips for reducing in-line testing in a semiconductor manufacturing line | Xu Ouyang, Hargurpreet Singh, Yunsheng Song, Stephen Wu | 2010-03-23 |