Issued Patents All Time
Showing 301–325 of 471 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6524941 | Sub-minimum wiring structure | Jack A. Mandelman | 2003-02-25 |
| 6524908 | Method for forming refractory metal-silicon-nitrogen capacitors and structures formed | Cyril Cabral, Jr., Lawrence A. Clevenger, Keith Kwong Hon Wong | 2003-02-25 |
| 6512683 | System and method for increasing the speed of memories | Li-Kong Wang, Toshiaki Kirihata | 2003-01-28 |
| 6512275 | Semiconductor integrated circuits | Jack A. Mandelman | 2003-01-28 |
| 6509612 | High dielectric constant materials as gate dielectrics (insulators) | Lawrence A. Clevenger, Carl Radens, Joseph F. Shepard, Jr. | 2003-01-21 |
| 6507237 | Low-power DC voltage generator system | Rajiv V. Joshi, Russell J. Houghton, Wayne F. Ellis, Jeffrey H. Dreibelbis | 2003-01-14 |
| 6504173 | Dual gate FET and process | Li-Kong Wang | 2003-01-07 |
| 6504777 | Enhanced bitline equalization for hierarchical bitline architecture | Li-Kong Wang | 2003-01-07 |
| 6504204 | Compact dual-port DRAM architecture system and method for making same | Rajiv V. Joshi, Radens Carl | 2003-01-07 |
| 6495445 | Semi-sacrificial diamond for air dielectric formation | Lawrence A. Clevenger | 2002-12-17 |
| 6492662 | T-RAM structure having dual vertical devices and method for fabricating the same | Rajiv V. Joshi | 2002-12-10 |
| 6492227 | Method for fabricating flash memory device using dual damascene process | Li-Kong Wang, Wei Hwang | 2002-12-10 |
| 6469949 | Fuse latch array system for an embedded DRAM having a micro-cell architecture | Li-Kong Wang | 2002-10-22 |
| 6456521 | Hierarchical bitline DRAM architecture system | Rajiv V. Joshi | 2002-09-24 |
| 6452855 | DRAM array interchangeable between single-cell and twin-cell array operation | Rajiv V. Joshi, John A. Fifield, Wayne F. Ellis | 2002-09-17 |
| 6452110 | Patterning microelectronic features without using photoresists | Lawrence A. Clevenger, Carl Radens, Li-Kong Wang, Keith Kwong Hon Wong | 2002-09-17 |
| 6449202 | DRAM direct sensing scheme | Hiroyuki Akatsu, Jeremy K. Stephens, Daniel W. Storaska | 2002-09-10 |
| 6445638 | Folded-bitline dual-port DRAM architecture system | Rajiv V. Joshi, Radens Carl | 2002-09-03 |
| 6445626 | Column redundancy architecture system for an embedded DRAM | Rajiv V. Joshi, Gregory J. Fredeman | 2002-09-03 |
| 6441421 | High dielectric constant materials forming components of DRAM storage cells | Lawrence A. Clevenger, Carl Radens, Joseph F. Shepard, Jr. | 2002-08-27 |
| 6437623 | Data retention registers | Wei Hwang, Stephen V. Kosonocky, Li-Kong Wang | 2002-08-20 |
| 6434076 | Refresh control circuit for low-power SRAM applications | John E. Andersen, Stephen V. Kosonocky, Li-Kong Wang | 2002-08-13 |
| 6433397 | N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same | Lawrence A. Clevenger, Rama Divakaruni, Yujun Li | 2002-08-13 |
| 6426914 | Floating wordline using a dynamic row decoder and bitline VDD precharge | Robert H. Dennard, Toshiaki Kirihata | 2002-07-30 |
| 6426903 | Redundancy arrangement using a focused ion beam | Lawrence A. Clevenger, Li-Kong Wang, Keith Kwong Hon Wong | 2002-07-30 |