Issued Patents All Time
Showing 26–50 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7790522 | Defect-free hybrid orientation technology for semiconductor devices | Rajiv V. Joshi, Xu Ouyang | 2010-09-07 |
| 7777306 | Defect-free hybrid orientation technology for semiconductor devices | Rajiv V. Joshi, Xu Ouyang | 2010-08-17 |
| 7772649 | SOI field effect transistor with a back gate for modulating a floating body | Kangguo Cheng, Jack A. Mandelman, Carl Radens, William R. Tonti | 2010-08-10 |
| 7732922 | Simultaneous grain modulation for BEOL applications | Chih-Chao Yang, Rajiv V. Joshi | 2010-06-08 |
| 7726010 | Method of forming a micro-electromechanical (MEMS) switch | Lawrence A. Clevenger, Timothy J. Dalton, Carl Radens, Keith Kwong Hon Wong, Chih-Chao Yang | 2010-06-01 |
| 7727888 | Interconnect structure and method for forming the same | Chih-Chao Yang, Rajiv V. Joshi | 2010-06-01 |
| 7728371 | SOI CMOS compatible multiplanar capacitor | Kangguo Cheng, Jack A. Mandelman, William R. Tonti | 2010-06-01 |
| 7709365 | CMOS well structure and method of forming the same | Wilfried E. Haensch, Terence B. Hook, Rajiv V. Joshi, Werner Rausch | 2010-05-04 |
| 7692308 | Microelectronic circuit structure with layered low dielectric constant regions | Lawrence A. Clevenger, Matthew E. Colburn, Wai-Kin Li | 2010-04-06 |
| 7694243 | Avoiding device stressing | Hibourahima Camara, James D. Rockrohr, Karl D. Selander, Huihao Xu, Steven J. Zier | 2010-04-06 |
| 7675342 | On-chip electrically alterable resistor | Brian L. Ji, Chung H. Lam | 2010-03-09 |
| 7676775 | Method to determine the root causes of failure patterns by using spatial correlation of tester data | Howard H. Chen, Katherine V. Hawkins, Fook-Luen Heng, Xu Ouyang | 2010-03-09 |
| 7660350 | High-speed multi-mode receiver | Brian L. Ji, James S. Mason, Karl D. Selander, Michael A. Soma, Steven J. Zier | 2010-02-09 |
| 7657995 | Method of fabricating a microelectromechanical system (MEMS) switch | Timothy J. Dalton, Lawrence A. Clevenger, Carl Radens, Kwong Hon Wong, Chih-Chao Yang | 2010-02-09 |
| 7651892 | Electrical programmable metal resistor | Chih-Chao Yang, Lawrence A. Clevenger, James J. Demarest, Carl Radens | 2010-01-26 |
| 7566599 | High performance FET with elevated source/drain region | Rama Divakaruni, Rajiv V. Joshi, Carl Radens | 2009-07-28 |
| 7528065 | Structure and method for MOSFET gate electrode landing pad | Lawrence A. Clevenger, Timothy J. Dalton, Carl Radens, Kwong Hon Wong, Chih-Chao Yang | 2009-05-05 |
| 7521760 | Integrated circuit chip with FETs having mixed body thickness and method of manufacture thereof | Rajiv V. Joshi, Oleg Gluschenkov | 2009-04-21 |
| 7488677 | Interconnect structures with encasing cap and methods of making thereof | Kwong Hon Wong, Timothy J. Dalton, Carol Radens, Chih-Chao Yang, Lawrence A. Clevenger +1 more | 2009-02-10 |
| 7485567 | Microelectronic circuit structure with layered low dielectric constant regions and method of forming same | Lawrence A. Clevenger, Matthew E. Colburn, Wai-Kin Li | 2009-02-03 |
| 7470929 | Fuse/anti-fuse structure and methods of making and programming same | Rajiv V. Joshi, Jack A. Mandelman, Chih-Chao Yang | 2008-12-30 |
| 7439172 | Circuit structure with low dielectric constant regions and method of forming same | Lawrence A. Clevenger, Matthew E. Colburn, Wai-Kin Li | 2008-10-21 |
| 7435674 | Dielectric interconnect structures and methods for forming the same | Chih-Chao Yang, Rajiv V. Joshi | 2008-10-14 |
| 7409019 | High Speed Multi-Mode Receiver with adaptive receiver equalization and controllable transmitter pre-distortion | Brian L. Ji, James S. Mason, Karl D. Selander, Michael A. Sorna, Steven J. Zier | 2008-08-05 |
| 7402463 | Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application | Chih-Chao Yang, Lawrence A. Clevenger, Timothy J. Dalton, Nicholas C. M. Fuller | 2008-07-22 |