Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
KC

Kangguo Cheng

IBM: 2575 patents #1 of 70,183Top 1%
Globalfoundries: 269 patents #3 of 4,424Top 1%
TETessera: 34 patents #14 of 271Top 6%
SSStmicroelectronics Sa: 19 patents #57 of 1,676Top 4%
ASAdeia Semiconductor Solutions: 13 patents #1 of 57Top 2%
ETElpis Technologies: 12 patents #1 of 121Top 1%
CEA: 6 patents #716 of 7,956Top 9%
GUGlobalfoundries U.S.: 5 patents #206 of 665Top 35%
Samsung: 5 patents #22,466 of 75,807Top 30%
RERenesas Electronics: 4 patents #1,016 of 4,529Top 25%
IBInternational Business: 1 patents #4 of 119Top 4%
Schenectady, NY: #1 of 1,353 inventorsTop 1%
New York: #1 of 115,490 inventorsTop 1%
Overall (All Time): #5 of 4,157,543Top 1%
2819 Patents All Time

Issued Patents All Time

Showing 2,551–2,575 of 2,819 patents

Patent #TitleCo-InventorsDate
8546228 Strained thin body CMOS device having vertically raised source/drain stressors with single spacer Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi 2013-10-01
8546209 Replacement metal gate processing with reduced interlevel dielectric layer etch rate Junli Wang, Keith Kwong Hon Wong, Chih-Chao Yang 2013-10-01
8541274 Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed after source/drain formation Ruilong Xie, Xiuyu Cai, Ali Khakifirooz 2013-09-24
8536632 FinFET with reduced gate to fin overlay sensitivity Louis L. Hsu, Jack A. Mandelman, John E. Sheets, II 2013-09-17
8536650 Strained ultra-thin SOI transistor formed by replacement gate Junedong Lee 2013-09-17
8536032 Formation of embedded stressor through ion implantation Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi 2013-09-17
8530974 CMOS structure having multiple threshold voltage devices Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni 2013-09-10
8530971 Borderless contacts for semiconductor devices Bruce B. Doris, Keith Kwong Hon Wong 2013-09-10
8525186 Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (SOI) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor Johnathan E. Faltermeier, Toshiharu Furukawa, Xuefeng Hua 2013-09-03
8525292 SOI device with DTI and STI Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni 2013-09-03
8525263 Programmable high-k/metal gate memory device Roger A. Booth, Jr., Chandrasekharan Kothandaraman, Chengwen Pei 2013-09-03
8524592 Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices Ruilong Xie, Xiuyu Cai, Ali Khakifirooz 2013-09-03
8525235 Multiplying pattern density by single sidewall imaging transfer Bruce B. Doris, Ying Zhang 2013-09-03
8518767 FinFET with reduced gate to fin overlay sensitivity Louis L. Hsu, Jack A. Mandelman, John E. Sheets, II 2013-08-27
8513765 Formation method and structure for a well-controlled metallic source/drain semiconductor device Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi 2013-08-20
8513723 Method and structure for forming high performance MOS capacitor along with fully depleted semiconductor on insulator devices on the same chip Roger A. Booth, Jr., Bruce B. Doris, Ghavam G. Shahidi 2013-08-20
8507354 On-chip capacitors in combination with CMOS devices on extremely thin semiconductor on insulator (ETSOI) substrates Thomas N. Adam, Ali Khakifirooz, Alexander Reznieck 2013-08-13
8507989 Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance Ali Khakifirooz, Bruce B. Doris 2013-08-13
8492839 Same-chip multicharacteristic semiconductor structures Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi 2013-07-23
8492821 Enhanced capacitance trench capacitor Byeong Y. Kim, Munir D. Naeem, James P. Norum 2013-07-23
8492817 Highly scalable trench capacitor Anne Marie Ebert, Johnathan E. Faltermeier 2013-07-23
8492811 Self-aligned strap for embedded capacitor and replacement gate devices Roger A. Booth, Jr., Joseph Ervin, Chengwen Pei, Geng Wang 2013-07-23
8492241 Method for simultaneously forming a through silicon via and a deep trench structure Mukta G. Farooq, Louis L. Hsu 2013-07-23
8492854 Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Christian Lavoie 2013-07-23
8486776 Strained devices, methods of manufacture and design structures Stephen W. Bedell, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Katherine L. Saenger 2013-07-16