Issued Patents All Time
Showing 151–175 of 178 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6127866 | Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays | Albert M. Chu, Jason Rotella, Jean-Marc Dortu | 2000-10-03 |
| 6118318 | Self biased differential amplifier with hysteresis | Lawrence G. Heller | 2000-09-12 |
| 5909400 | Three device BICMOS gain cell | Claude L. Bertin, Russell J. Houghton, Christopher P. Miller, William R. Tonti | 1999-06-01 |
| 5880988 | Reference potential for sensing data in electronic storage element | Claude L. Bertin, Russell J. Houghton, Christopher P. Miller, William R. Tonti | 1999-03-09 |
| 5873053 | On-chip thermometry for control of chip operating temperature | Wilbur D. Pricer, Wendell P. Noble, John E. Gersbach | 1999-02-16 |
| 5796270 | Self-timed driver circuit | Glenn P. Giacalone, Peter Joel Jenkins | 1998-08-18 |
| 5761114 | Multi-level storage gain cell with stepline | Claude L. Bertin, Russell J. Houghton, Christopher P. Miller, William R. Tonti | 1998-06-02 |
| 5757693 | Gain memory cell with diode | Russell J. Houghton, Claude L. Bertin, Christopher P. Miller, William R. Tonti | 1998-05-26 |
| 5682394 | Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature | Robert M. Blake, Douglas Craig Bossen, Chin-Long Chen, Howard L. Kalter | 1997-10-28 |
| 5675774 | "Circuit element on a single ended interconnection for generating a logical output finish/clock signal when detecting a state change to logical ""1 or 0""." | Lawrence G. Heller | 1997-10-07 |
| 5638385 | Fast check bit write for a semiconductor memory | Duane E. Galbi, Hsing-San Lee | 1997-06-10 |
| 5633605 | Dynamic bus with singular central precharge | Jeffrey S. Zimmerman, Christopher P. Miller, Robert E. Busch | 1997-05-27 |
| 5604755 | Memory system reset circuit | Claude L. Bertin, Charles E. Drake, Erik L. Hedberg | 1997-02-18 |
| 5581567 | Dual level error detection and correction employing data subsets from previously corrected data | Chin-Long Chen, Howard L. Kalter, Willem B. van der Hoeven | 1996-12-03 |
| 5561694 | Self-timed driver circuit | Glenn P. Giacalone, Peter Joel Jenkins | 1996-10-01 |
| 5550488 | Self timed driver | Lawrence G. Heller | 1996-08-27 |
| 5535226 | On-chip ECC status | Charles E. Drake, Richard D. Wheeler, Barry Joe Wolford | 1996-07-09 |
| 5532622 | Multi-input transition detector with a single delay | Mark A. Beiley | 1996-07-02 |
| 5533036 | Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature | Robert M. Blake, Douglas Craig Bossen, Chin-Long Chen, Howard L. Kalter | 1996-07-02 |
| 5307356 | Interlocked on-chip ECC system | — | 1994-04-26 |
| 5260952 | Fault tolerant logic system | Kenneth E. Beilstein, Jr., Lawrence G. Heller, Hsing-San Lee, Charles H. Stapper | 1993-11-09 |
| 5228046 | Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature | Robert M. Blake, Douglas Craig Bossen, Chin-Long Chen, Howard L. Kalter | 1993-07-13 |
| 5134616 | Dynamic RAM with on-chip ECC and optimized bit and word redundancy | John E. Barth, Jr., Charles E. Drake, William Paul Hovis, Howard L. Kalter, Scott C. Lewis +3 more | 1992-07-28 |
| 5058115 | Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature | Robert M. Blake, Douglas Craig Bossen, Chin-Long Chen, Howard L. Kalter, Tin-Chee Lo | 1991-10-15 |
| 5031151 | Wordline drive inhibit circuit implementing worldline redundancy without an access time penalty | Howard L. Kalter, Christopher P. Miller, Steven W. Thomashot | 1991-07-09 |