Issued Patents All Time
Showing 126–150 of 216 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7525646 | Multiple pattern generator integration with single post expose bake station | Daniel Sullivan, Brain Neal Caldwell, Adam C. Smith | 2009-04-28 |
| 7507506 | Method and structure for creating a multilayer mask (MLM or MLR) using multiple write tools to minimize mask write and substrate costs | Brent A. Anderson | 2009-03-24 |
| 7494748 | Method for correction of defects in lithography masks | James W. Adkisson, Eric M. Coker, Christopher K. Magg, Anthony K. Stamper | 2009-02-24 |
| 7491476 | Photomask electrical monitor for production photomasks | Brent A. Anderson | 2009-02-17 |
| 7473523 | Systems and methods for modifying features in a semi-conductor device | Brent A. Anderson | 2009-01-06 |
| 7473970 | Concurrent fin-fet and thick body device fabrication | Wagdi W. Abadeer, Jeffrey S. Brown, David M. Fried, Robert J. Gauthier, Jr., Edward J. Nowak +1 more | 2009-01-06 |
| 7473946 | CMOS structure and method including multiple crystallographic planes | Brent A. Anderson, Edward J. Nowak | 2009-01-06 |
| 7393703 | Method for reducing within chip device parameter variations | Brent A. Anderson, Shahid Butt, Allen H. Gabor, Patrick Edward Lindo, Edward J. Nowak | 2008-07-01 |
| 7387937 | Thermal dissipation structures for FinFETs | Brent A. Anderson, Edward J. Nowak, William F. Clark, Jr. | 2008-06-17 |
| 7382036 | Doped single crystal silicon silicided eFuse | Edward J. Nowak, William R. Tonti, Richard Q. Williams | 2008-06-03 |
| 7368354 | Planar substrate devices integrated with FinFETs and method of manufacture | Brent A. Anderson, Edward J. Nowak | 2008-05-06 |
| 7361556 | Method of fabricating semiconductor side wall fin | James W. Adkisson, Paul D. Agnello, Arne Ballantine, Rama Divakaruni, Erin C. Jones +1 more | 2008-04-22 |
| 7301210 | Method and structure to process thick and thin fins and variable fin to fin spacing | Wagdi W. Abadeer, Jeffrey S. Brown, Kiran V. Chatty, Robert J. Gauthier, Jr., William R. Tonti | 2007-11-27 |
| 7297582 | Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions | Wagdi W. Abadeer, Jeffrey S. Brown, Robert J. Gauthier, Jr., William R. Tonti | 2007-11-20 |
| 7294440 | Method to selectively correct critical dimension errors in the semiconductor industry | Andrew J. Watts | 2007-11-13 |
| 7288445 | Double gated transistor and method of fabrication | Andres Bryant, Meikei Ieong, K. Paul Muller, Edward J. Nowak, David M. Fried | 2007-10-30 |
| 7268397 | Thermal dissipation structures for finfets | Brent A. Anderson, Edward J. Nowak, William F. Clark, Jr. | 2007-09-11 |
| 7265417 | Method of fabricating semiconductor side wall fin | James W. Adkisson, Paul D. Agnello, Arne Ballantine, Rama Divakaruni, Erin C. Jones +1 more | 2007-09-04 |
| 7247908 | Method of fabricating a FinFET | Brent A. Anderson, Edward J. Nowak | 2007-07-24 |
| 7224029 | Method and structure to create multiple device widths in FinFET technology in both bulk and SOI | Brent A. Anderson, Edward J. Nowak | 2007-05-29 |
| 7211356 | Method of patterning a substrate by feeding mask defect data forward for subsequent correction | Andrew J. Watts | 2007-05-01 |
| 7200257 | Structure and methodology for fabrication and inspection of photomasks | Andrew J. Watts | 2007-04-03 |
| 7188322 | Circuit layout methodology using a shape processing application | John M. Cohn, Jason D. Hibbeler, Anthony K. Stamper | 2007-03-06 |
| 7173303 | FIN field effect transistor with self-aligned gate | Jeffrey P. Gambino, Jerome B. Lasky | 2007-02-06 |
| 7163864 | Method of fabricating semiconductor side wall fin | James W. Adkisson, Paul D. Agnello, Arne Ballantine, Rama Divakaruni, Erin C. Jones +1 more | 2007-01-16 |