Issued Patents All Time
Showing 51–75 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6521949 | SOI transistor with polysilicon seed | Tze-Chiang Chen, K. Paul Muller, Edward J. Nowak, Ghavam G. Shahidi | 2003-02-18 |
| 6433587 | SOI CMOS dynamic circuits having threshold voltage control | Kerry Bernstein, Michael Hargrove, Norman J. Rohrer, Peter Smeys | 2002-08-13 |
| 6432754 | Double SOI device with recess etch and epitaxy | Tze-Chiang Chen, K. Paul Muller, Edward J. Nowak, Devendra K. Sadana, Ghavam G. Shahidi | 2002-08-13 |
| 6429084 | MOS transistors with raised sources and drains | Heemyong Park, Dominic J. Schepis | 2002-08-06 |
| 6424011 | Mixed memory integration with NVRAM, dram and sram cell structures on same substrate | Louis L. Hsu, Jack A. Mandelman | 2002-07-23 |
| 6410369 | Soi-body selective link method and apparatus | Roy C. Flaker, Louis L. Hsu, Jack A. Mandelman | 2002-06-25 |
| 6404686 | High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatus | Anthony Gus Aipperspach, Todd A. Christensen, Douglas M. Dewanz, Jente B. Kuang | 2002-06-11 |
| 6352882 | Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation | Louis L. Hsu, Jack A. Mandelman | 2002-03-05 |
| 6344671 | Pair of FETs including a shared SOI body contact and the method of forming the FETs | Jack A. Mandelman, Michael Hargrove, Peter Smeys, Norman J. Rohrer | 2002-02-05 |
| 6320237 | Decoupling capacitor structure | Harold W. Chase, Stephen L. Runyon | 2001-11-20 |
| 6259126 | Low cost mixed memory integration with FERAM | Louis L. Hsu, Jack A. Mandelman | 2001-07-10 |
| 6252429 | Method and apparatus for improving device matching and switching point tolerance in silicon-on-insulator cross-coupled circuits | Ching-Te Chuang, Jente B. Kuang | 2001-06-26 |
| 6232173 | Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure | Louis L. Hsu, Jack A. Mandelman | 2001-05-15 |
| 6141632 | Method for use in simulation of an SOI device | George E. Smith, III, Paul D. Muench, Lawrence F. Wagner, Jr., Timothy Walters | 2000-10-31 |
| 6141242 | Low cost mixed memory integration with substantially coplanar gate surfaces | Louis L. Hsu, Jack A. Mandelman | 2000-10-31 |
| 6136655 | Method of making low voltage active body semiconductor device | Claude L. Bertin, Jeffrey P. Gambino, Louis L. Hsu, Jack A. Mandelman | 2000-10-24 |
| 6133608 | SOI-body selective link method and apparatus | Roy C. Flaker, Louis L. Hsu, Jack A. Mandelman | 2000-10-17 |
| 6121661 | Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation | Louis L. Hsu, Jack A. Mandelman | 2000-09-19 |
| 6023577 | Method for use in simulation of an SOI device | George E. Smith, III, Lawrence F. Wagner, Jr., Timothy Walters | 2000-02-08 |
| 5998847 | Low voltage active body semiconductor device | Claude L. Bertin, Jeffrey P. Gambino, Louis L. Hsu, Jack A. Mandelman | 1999-12-07 |
| 5880991 | Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure | Louis L. Hsu, Jack A. Mandelman | 1999-03-09 |
| 5811857 | Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications | Louis L. Hsu, Jack A. Mandelman, Ghavam G. Shahidi, Steven H. Voldman | 1998-09-22 |
| 5784311 | Two-device memory cell on SOI for merged logic and memory applications | Bijan Davari, Louis L. Hsu, Jack A. Mandelman, Ghavam G. Shahidi | 1998-07-21 |
| 5770875 | Large value capacitor for SOI | Louis L. Hsu, Jack A. Mandelman, William R. Tonti | 1998-06-23 |
| 5770881 | SOI FET design to reduce transient bipolar current | Mario M. Pelella, Lawrence F. Wagner, Jr. | 1998-06-23 |