Issued Patents All Time
Showing 26–50 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8341450 | Continuous timing calibrated memory interface | Kun-Yung Chang, Hae-Chang Lee | 2012-12-25 |
| 8325861 | Drift cancellation technique for use in clock-forwarding architectures | Kun-Yung Chang | 2012-12-04 |
| 8121233 | Drift cancellation technique for use in clock-forwarding architectures | Kun-Yung Chang | 2012-02-21 |
| 7949041 | Methods and circuits for asymmetric distribution of channel equalization between devices | Jared L. Zerbe, Brian S. Leibowitz, Hae-Chang Lee, Jihong Ren, Qi Lin | 2011-05-24 |
| 7724852 | Drift cancellation technique for use in clock-forwarding architectures | Kun-Yung Chang | 2010-05-25 |
| 7307560 | Phase linearity test circuit | Xudong Shi | 2007-12-11 |
| 7163866 | SOI MOSFETS exhibiting reduced floating-body effects | Werner Rausch, Dominic J. Schepis, Ghavam G. Shahidi | 2007-01-16 |
| 7075153 | Grounded body SOI SRAM cell | Andres Bryant, Peter E. Cottrell, Robert J. Gauthier, Jr., Randy W. Mann, Edward J. Nowak +1 more | 2006-07-11 |
| 7009258 | Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ doped selective amorphous silicon | Heemyong Park, Jack A. Mandelman | 2006-03-07 |
| 6940130 | Body contact MOSFET | Andres Bryant, Peter E. Cottrell, John J. Ellis-Monaghan, Robert J. Gauthier, Jr., Edward J. Nowak +1 more | 2005-09-06 |
| 6906354 | T-RAM cell having a buried vertical thyristor and a pseudo-TFT transfer gate and method for fabricating the same | Louis L. Hsu, Rajiv V. Joshi | 2005-06-14 |
| 6808974 | CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regions | Heemyong Park, Dominic J. Schepis | 2004-10-26 |
| 6777304 | Method for producing an integrated circuit capacitor | Harold W. Chase, Stephen L. Runyon | 2004-08-17 |
| 6734109 | Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ doped selective amorphous silicon | Heemyong Park, Jack A. Mandelman | 2004-05-11 |
| 6713791 | T-RAM array having a planar cell structure and method for fabricating the same | Louis L. Hsu, Rajiv V. Joshi, Dan Moy, Werner Rausch, James A. Culp | 2004-03-30 |
| 6714476 | Memory array with dual wordline operation | Louis L. Hsu, Rajiv V. Joshi | 2004-03-30 |
| 6686629 | SOI MOSFETS exhibiting reduced floating-body effects | Werner Rausch, Dominic J. Schepis, Ghavam G. Shahidi | 2004-02-03 |
| 6677645 | Body contact MOSFET | Andres Bryant, Peter E. Cottrell, John J. Ellis-Monaghan, Robert J. Gauthier, Jr., Edward J. Nowak +1 more | 2004-01-13 |
| 6657261 | Ground-plane device with back oxide topography | Tze-Chiang Chen, K. Paul Muller, Edward J. Nowak, Devendra K. Sadana, Ghavam G. Shahidi | 2003-12-02 |
| 6646305 | Grounded body SOI SRAM cell | Andres Bryant, Peter E. Cottrell, Robert J. Gauthier, Jr., Randy W. Mann, Edward J. Nowak +1 more | 2003-11-11 |
| 6613615 | Pair of FETs including a shared SOI body contact and the method of forming the FETs | Jack A. Mandelman, Michael Hargrove, Peter Smeys, Norman J. Rohrer | 2003-09-02 |
| 6566198 | CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture | Heemyong Park, Atul Ajmera, Ghavam G. Shahidi | 2003-05-20 |
| 6562666 | Integrated circuits with reduced substrate capacitance | Heemyong Park, Jack A. Mandelman, Ghavam G. Shahidi, Lawrence F. Wagner, Jr. | 2003-05-13 |
| 6552398 | T-Ram array having a planar cell structure and method for fabricating the same | Louis L. Hsu, Rajiv V. Joshi | 2003-04-22 |
| 6549450 | Method and system for improving the performance on SOI memory arrays in an SRAM architecture system | Louis L. Hsu, Rajiv V. Joshi, Mary J. Saccamango | 2003-04-15 |