Issued Patents All Time
Showing 26–50 of 401 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11756996 | Formation of wrap-around-contact for gate-all-around nanosheet FET | Takashi Ando, Pouya Hashemi, Alexander Reznicek, Jingyun Zhang | 2023-09-12 |
| 11756960 | Multi-threshold voltage gate-all-around transistors | Jingyun Zhang, Takashi Ando | 2023-09-12 |
| 11742409 | Replacement-channel fabrication of III-V nanosheet devices | Jingyun Zhang, Chun Wing Yeung, Robin Hsin Kuo Chao, Heng Wu | 2023-08-29 |
| 11682471 | Dual damascene crossbar array for disabling a defective resistive switching device in the array | Joseph F. Maniscalco, Oscar van der Straten, Koichi Motoyama, Seyoung Kim | 2023-06-20 |
| 11659780 | Phase change memory structure with efficient heating system | Injo Ok, Alexander Reznicek, Soon-Cheon Seo | 2023-05-23 |
| 11600593 | Die bonding apparatus and method and substrate bonding apparatus and method | Hanglim Lee, Jungsuk Goh, Kwangsup Kim, Doyeon KIM, Minyoung KIM +5 more | 2023-03-07 |
| 11594676 | Resistive random-access memory | Kangguo Cheng, Juntao Li, Peng Xu | 2023-02-28 |
| 11588103 | Resistive memory array | Youngseok Kim, Timothy Mathew Philip, Soon-Cheon Seo, Injo Ok, Alexander Reznicek | 2023-02-21 |
| 11587837 | Oxygen vacancy passivation in high-k dielectrics for vertical transport field effect transistor | Takashi Ando, Alexander Reznicek, Jingyun Zhang | 2023-02-21 |
| 11527574 | Stacked resistive memory with individual switch control | Takashi Ando, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek | 2022-12-13 |
| 11527616 | Vertical transport CMOS transistors with asymmetric threshold voltage | Takashi Ando, Jingyun Zhang, Alexander Reznicek | 2022-12-13 |
| 11521927 | Buried power rail for scaled vertical transport field effect transistor | Ruilong Xie, Junli Wang, Alexander Reznicek | 2022-12-06 |
| 11515214 | Threshold voltage adjustment by inner spacer material selection | Takashi Ando, Jingyun Zhang, Pouya Hashemi | 2022-11-29 |
| 11515217 | Complementary metal oxide semiconductor device having fin field effect transistors with a common metal gate | Takashi Ando, Pouya Hashemi, Jingyun Zhang | 2022-11-29 |
| 11495669 | Full air-gap spacers for gate-all-around nanosheet field effect transistors | Takashi Ando, Pouya Hashemi, Alexander Reznicek, Jingyun Zhang | 2022-11-08 |
| 11495668 | Full air-gap spacers for gate-all-around nanosheet field effect transistors | Takashi Ando, Pouya Hashemi, Alexander Reznicek, Jingyun Zhang | 2022-11-08 |
| 11482612 | Vertical transistor having bottom spacers on source/drain regions with different heights along junction region | Shogo Mochizuki, Kangguo Cheng, Juntao Li | 2022-10-25 |
| 11476362 | Vertical transistors with various gate lengths | Juntao Li, Kangguo Cheng, Shogo Mochizuki | 2022-10-18 |
| 11444165 | Asymmetric threshold voltages in semiconductor devices | Takashi Ando, Alexander Reznicek, Jingyun Zhang, Pouya Hashemi | 2022-09-13 |
| 11430660 | Confined work function material for gate-all around transistor devices | Jingyun Zhang, Takashi Ando, Alexander Reznicek, Pouya Hashemi | 2022-08-30 |
| 11430514 | Setting an upper bound on RRAM resistance | Youngseok Kim, Soon-Cheon Seo, Injo Ok, Alexander Reznicek | 2022-08-30 |
| 11424343 | Vertical fin field effect transistor devices with self-aligned source and drain junctions | Kangguo Cheng, Juntao Li, Shogo Mochizuki | 2022-08-23 |
| 11404581 | Wimpy vertical transport field effect transistor with dipole liners | Alexander Reznicek, Xin Miao, Jingyun Zhang | 2022-08-02 |
| 11387342 | Multi threshold voltage for nanosheet | Jingyun Zhang, Takashi Ando, Alexander Reznicek | 2022-07-12 |
| 11380778 | Vertical fin field effect transistor devices with self-aligned source and drain junctions | Kangguo Cheng, Juntao Li, Shogo Mochizuki | 2022-07-05 |