Issued Patents All Time
Showing 26–50 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7289370 | Methods and apparatus for accessing memory | Chad A. Adams, Juergen Pille, Otto Wagner | 2007-10-30 |
| 7242233 | Simplified method for limiting clock pulse width | David William Boerstler, Eskinder Hailu | 2007-07-10 |
| 7239559 | Methods and apparatus for accessing memory | Chad A. Adams | 2007-07-03 |
| 7224594 | Glitch protect valid cell and method for maintaining a desired state value | Derick G. Behrends, Chad A. Adams, Ryan Charles Kivimagi, Robert N. Krentler | 2007-05-29 |
| 7206236 | Array redundancy supporting multiple independent repairs | Todd A. Christensen, Elizabeth L. Gerhard, George Paulik | 2007-04-17 |
| 7161390 | Dynamic latching logic structure with static interfaces for implementing improved data setup time | Peter Thomas Freiburger | 2007-01-09 |
| 7092281 | Method and apparatus for reducing soft error rate in SRAM arrays using elevated SRAM voltage during periods of low activity | David H. Allen | 2006-08-15 |
| 7009905 | Method and apparatus to reduce bias temperature instability (BTI) effects | William Paul Hovis, Terrance Wayne Kueper, John E. Sheets, II | 2006-03-07 |
| 6901003 | Lower power and reduced device split local and continuous bitline for domino read SRAMs | Chad A. Adams, Todd A. Christensen, Peter Thomas Freiburger | 2005-05-31 |
| 6868033 | Dual array read port functionality from a one port SRAM | David Arnold Luick | 2005-03-15 |
| 6833737 | SOI sense amplifier method and apparatus | — | 2004-12-21 |
| 6737685 | Compact SRAM cell layout for implementing one-port or two-port operation | Donald W. Plass | 2004-05-18 |
| 6661726 | Multiple mode elastic data transfer interface | Derick G. Behrends | 2003-12-09 |
| 6657886 | Split local and continuous bitline for fast domino read SRAM | Chad A. Adams, Todd A. Christensen, Peter Thomas Freiburger | 2003-12-02 |
| 6643804 | Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under test | Todd A. Christensen, Douglas M. Dewanz | 2003-11-04 |
| 6635518 | SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies | Jente B. Kuang, John E. Sheets, II, Daniel Stasiak | 2003-10-21 |
| 6629236 | Master-slave latch circuit for multithreaded processing | Merwin H. Alferness, Gregory J. Uhlmann | 2003-09-30 |
| 6570433 | Laser fuseblow protection method for silicon on insulator (SOI) transistors | Todd A. Christensen | 2003-05-27 |
| 6538522 | Method and ring oscillator for evaluating dynamic circuits | Todd A. Christensen, Peter Thomas Freiburger, David M. Friend, Nghia V. Phan | 2003-03-25 |
| 6509236 | Laser fuseblow protection method for silicon on insulator (SOI) transistors | Todd A. Christensen | 2003-01-21 |
| 6404686 | High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatus | Fariborz Assaderaghi, Todd A. Christensen, Douglas M. Dewanz, Jente B. Kuang | 2002-06-11 |
| 6275427 | Stability test for silicon on insulator SRAM memory cells utilizing disturb operations to stress memory cells under test | Todd A. Christensen, Douglas M. Dewanz | 2001-08-14 |
| 6260164 | SRAM that can be clocked on either clock phase | Leland Leslie Day, Paul Allen Ganfield, Charles L. Johnson | 2001-07-10 |
| 6247166 | Method and apparatus for assembling array and datapath macros | Peter Thomas Freiburger | 2001-06-12 |
| 6205063 | Apparatus and method for efficiently correcting defects in memory circuits | Sheldon B. Levenstein | 2001-03-20 |