Issued Patents All Time
Showing 626–650 of 1,279 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10069008 | Vertical transistor pass gate device | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-09-04 |
| 10062643 | Nickel-silicon fuse for FinFET structures | Kangguo Cheng, Keith E. Fogel, Pouya Hashemi | 2018-08-28 |
| 10056379 | Low voltage (power) junction FET with all-around junction gate | Karthik Balakrishnan, Bahman Hekmatshoartabari, Jeng-Bang Yau | 2018-08-21 |
| 10056329 | Programmable buried antifuse | Praneet Adusumilli, Keith E. Fogel, Oscar van der Straten | 2018-08-21 |
| 10056254 | Methods for removal of selected nanowires in stacked gate all around architecture | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-08-21 |
| 10056503 | MIS capacitor for finned semiconductor structure | Keith E. Fogel, Pouya Hashemi, Shogo Mochizuki | 2018-08-21 |
| 10056482 | Implementation of long-channel thick-oxide devices in vertical transistor flow | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-08-21 |
| 10056474 | Semiconductor structures having increased channel strain using fin release in gate regions | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Kern Rim | 2018-08-21 |
| 10056391 | Vertically stacked FinFET fuse | Praneet Adusumilli, Oscar van der Straten | 2018-08-21 |
| 10049945 | Forming a CMOS with dual strained channels | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2018-08-14 |
| 10049980 | Low resistance seed enhancement spacers for voidless interconnect structures | Praneet Adusumilli, Joseph F. Maniscalco, Oscar van der Straten | 2018-08-14 |
| 10050143 | Integrated ferroelectric capacitor/ field effect transistor structure | Takashi Ando, Pouya Hashemi | 2018-08-14 |
| 10043825 | Lateral bipolar junction transistor with multiple base lengths | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2018-08-07 |
| 10043878 | Vertical field-effect-transistors having multiple threshold voltages | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-08-07 |
| 10038050 | FinFET resistor and method to fabricate same | Praneet Adusumilli, Keith E. Fogel, Oscar van der Straten | 2018-07-31 |
| 10038053 | Methods for removal of selected nanowires in stacked gate all around architecture | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-07-31 |
| 10037942 | Low resistance contact structures for trench structures | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2018-07-31 |
| 10032870 | Low defect III-V semiconductor template on porous silicon | Joel P. de Souza, Keith E. Fogel, Dominic J. Schepis | 2018-07-24 |
| 10032721 | Low resistance contact structures for trench structures | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2018-07-24 |
| 10020398 | Stress induction in 3D device channel using elastic relaxation of high stress material | Kangguo Cheng, Nicolas Loubet, Xin Miao | 2018-07-10 |
| 10020384 | Forming a fin using double trench epitaxy | Veeraraghavan S. Basker, Pouya Hashemi, Shogo Mochizuki | 2018-07-10 |
| 10014371 | Stressed nanowire stack for field effect transistor | Martin M. Frank, Pouya Hashemi, Ali Khakifirooz | 2018-07-03 |
| 10014322 | Local SOI fins with multiple heights | Kangguo Cheng, Joel P. de Souza, Ali Khakifirooz, Dominic J. Schepis | 2018-07-03 |
| 10011920 | Low-temperature selective epitaxial growth of silicon for device integration | Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi | 2018-07-03 |
| 10008596 | Channel-last replacement metal-gate vertical field effect transistor | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-06-26 |