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Systems and methods for designing a discrete device product |
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Superjunction structures for power devices |
Joseph A. Yedinak, Jaegil LEE, Chongman Yun, Praveen Muraleedharan Shenoy |
2017-03-14 |
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Superjunction structures for power devices |
Jaegil LEE, Chongman Yun, Hocheol Jang, Praveen Muraleedharan Shenoy, Dwayne S. Reichl +1 more |
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Superjunction structures for power devices and methods of manufacture |
Joseph A. Yedinak, Jaegil LEE, Hamza Yilmaz, Chongman Yun |
2014-07-22 |
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High density FET with integrated Schottky |
Paul Thorup |
2014-04-01 |
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Field effect transistor and schottky diode structures |
Christopher Boguslaw Kocon, Steven Sapp, Paul Thorup, Dean E. Probst, Robert Herrick +3 more |
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Structure related to a thick bottom dielectric (TBD) for trench-gate devices |
James Pan |
2014-03-11 |
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Double layer metal (DLM) power MOSFET |
Rohit Dikshit, Mark L. Rinehimer, Michael D. Gruenhagen, Joseph A. Yedinak, Tracie Petersen +3 more |
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Trench power MOSFET with reduced on-resistance |
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2013-01-29 |
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Wide bandgap device in parallel with a device that has a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device |
Joseph A. Yedinak, Richard L. Woodin, Praveen Muralheedaran Shenoy, Kwanghoon Oh, Chongman Yun |
2013-01-22 |
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Rugged semiconductor device architecture |
Gary M. Dolny, Richard L. Woodin, Carl Anthony Witt, Joseph Shovlin |
2012-02-28 |
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Wide bandgap device in parallel with a device that has a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device |
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2010-12-28 |
| 7586156 |
Wide bandgap device in parallel with a device that has a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device |
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2009-09-08 |
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Method of forming trench gate field effect transistor with recessed mesas |
Steven Sapp, Hamza Yilmaz, Daniel Calafut |
2009-03-17 |
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Method of making a MOS-gated semiconductor device with a single diffusion |
John Manning Savidge Neilson, Linda S. Brush, Frank Stensney, John L. Benjamin, Anup Bhalla +4 more |
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Method of fabricating UMOS semiconductor devices using a self-aligned, reduced mask process |
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Method of making MOS-gated semiconductor devices |
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1995-06-06 |
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Power FET with gate segments covering drain regions disposed in a hexagonal pattern |
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1994-06-21 |
| 5317184 |
Device and method for improving current carrying capability in a semiconductor device |
— |
1994-05-31 |