Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5468668 | Method of forming MOS-gated semiconductor devices having mesh geometry pattern | John Manning Savidge Neilson, Carl F. Wheatley, Jr., Victor A. K. Temple | 1995-11-21 |
| 5399892 | Mesh geometry for MOS-gated semiconductor devices | John Manning Savidge Neilson, Carl F. Wheatley, Jr., Victor A. K. Temple | 1995-03-21 |
| 5323036 | Power FET with gate segments covering drain regions disposed in a hexagonal pattern | John Manning Savidge Neilson, Joseph A. Yedinak, Christopher L. Rexer | 1994-06-21 |
| 5218220 | Power FET having reduced threshold voltage | John Manning Savidge Neilson, Joseph A. Yedinak | 1993-06-08 |
| 5164802 | Power VDMOSFET with schottky on lightly doped drain of lateral driver FET | Joseph A. Yedinak, John Manning Savidge Neilson, Robert S. Wrathall, Jeffrey G. Mansmann, Claire E. Jackoski | 1992-11-17 |
| 5079608 | Power MOSFET transistor circuit with active clamp | Paul J. Wodarczyk, John Manning Savidge Neilson, Joseph A. Yedinak | 1992-01-07 |