Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6638826 | Power MOS device with buried gate | Jun Zeng, Gary M. Dolny, Christopher Boguslaw Kocon | 2003-10-28 |
| 6455379 | Power trench transistor device source region formation using silicon spacer | Jun Zeng, John J. Hackenberg, Jack H. Linn, George V. Rouse | 2002-09-24 |
| 6445035 | Power MOS device with buried gate and groove | Jun Zeng, Gary M. Dolny, Christopher Boguslaw Kocon | 2002-09-03 |
| 6373098 | Trench-gated device having trench walls formed by selective epitaxial growth and process for forming device | Jun Zeng, Christopher Boguslaw Kocon | 2002-04-16 |
| 6246090 | Power trench transistor device source region formation using silicon spacer | Jun Zeng, John J. Hackenberg, Jack H. Linn, George V. Rouse | 2001-06-12 |
| 6215168 | Doubly graded junction termination extension for edge passivation of semiconductor devices | John Neilson | 2001-04-10 |
| 6080614 | Method of making a MOS-gated semiconductor device with a single diffusion | John Manning Savidge Neilson, Frank Stensney, John L. Benjamin, Anup Bhalla, Christopher L. Rexer +4 more | 2000-06-27 |
| 5877044 | Method of making MOS-gated semiconductor devices | John Manning Savidge Neilson, Christopher Boguslaw Kocon, Richard Stokes, John L. Benjamin, Louise Skurkey +1 more | 1999-03-02 |