Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8492837 | Reduced process sensitivity of electrode-semiconductor rectifiers | Joseph A. Yedinak, Mark L. Rinehimer, Thomas E. Grebs | 2013-07-23 |
| 8227855 | Semiconductor devices with stable and controlled avalanche characteristics and methods of fabricating the same | Joseph A. Yedinak, Mark L. Rinehimer, Thomas E. Grebs | 2012-07-24 |
| 8148749 | Trench-shielded semiconductor device | Thomas E. Grebs, Mark L. Rinehimer, Joseph A. Yedinak, Dean E. Probst, Gary M. Dolny | 2012-04-03 |
| 8049276 | Reduced process sensitivity of electrode-semiconductor rectifiers | Joseph A. Yedinak, Mark L. Rinehimer, Thomas E. Grebs | 2011-11-01 |
| 7332750 | Power semiconductor device with improved unclamped inductive switching capability and process for forming same | Jifa Hao, Randall L. Case, Jae Jun YUN | 2008-02-19 |
| 6465325 | Process for depositing and planarizing BPSG for dense trench MOSFET application | Rodney S. Ridley, Frank Stensney, Jack H. Linn | 2002-10-15 |
| 6358825 | Process for controlling lifetime in a P-I-N diode and for forming diode with improved lifetime control | Jifa Hao, Randall L. Case | 2002-03-19 |
| 6080614 | Method of making a MOS-gated semiconductor device with a single diffusion | John Manning Savidge Neilson, Linda S. Brush, Frank Stensney, Anup Bhalla, Christopher L. Rexer +4 more | 2000-06-27 |
| 6054369 | Lifetime control for semiconductor devices | John Manning Savidge Neilson, Maxime Zafrani | 2000-04-25 |
| 5877044 | Method of making MOS-gated semiconductor devices | John Manning Savidge Neilson, Christopher Boguslaw Kocon, Richard Stokes, Linda S. Brush, Louise Skurkey +1 more | 1999-03-02 |
| 4778776 | Passivation with a low oxygen interface | David W. Tong, William R. VanDell | 1988-10-18 |
| 4597822 | Method for making silicon wafers | William R. Van Dell | 1986-07-01 |