MV

Maud Vinet

CEA: 88 patents #1 of 7,956Top 1%
SS Stmicroelectronics Sa: 25 patents #442 of 4,662Top 10%
IBM: 11 patents #9,995 of 70,183Top 15%
Globalfoundries: 3 patents #1,029 of 4,424Top 25%
SS Stmicroelectronics (Crolles 2) Sas: 3 patents #150 of 529Top 30%
CN CNRS: 2 patents #1,756 of 11,908Top 15%
📍 Grenoble, NY: #1 of 14 inventorsTop 8%
Overall (All Time): #17,853 of 4,157,543Top 1%
90
Patents All Time

Issued Patents All Time

Showing 26–50 of 90 patents

Patent #TitleCo-InventorsDate
9673329 Method for manufacturing a fin MOS transistor Yves Morand, Romain Wacquez, Laurent Grenouillet, Yannick Le Tiec 2017-06-06
9634103 CMOS in situ doped flow with independently tunable spacer thickness Laurent Grenouillet, Qing Liu 2017-04-25
9601511 Low leakage dual STI integrated circuit including FDSOI transistors Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz, Yannick Le Tiec +1 more 2017-03-21
9570340 Method of etching a crystalline semiconductor material by ion implantation and then chemical etching based on hydrogen chloride Laurent Grenouillet, Romain Wacquez 2017-02-14
9570465 Dual STI integrated circuit including FDSOI transistors and method for manufacturing the same Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz, Yannick Le Tiec +1 more 2017-02-14
9502292 Dual shallow trench isolation liner for preventing electrical shorts Bruce B. Doris, Shom Ponoth, Prasanna Khare, Qing Liu, Nicolas Loubet 2016-11-22
9466664 Uniaxially-strained FD-SOI finFET Pierre Morin, Laurent Grenouillet, Ajey Poovannummoottil Jacob 2016-10-11
9443933 Matching of transistors Frédéric Allibert 2016-09-13
9437474 Method for fabricating microelectronic devices with isolation trenches partially formed under active regions Laurent Grenouillet, Yannick Le Tiec, Nicolas Loubet, Romain Wacquez 2016-09-06
9437475 Method for fabricating microelectronic devices with isolation trenches partially formed under active regions Sylvie Mignot, Romain Wacquez 2016-09-06
9425051 Method for producing a silicon-germanium film with variable germanium content Laurent Grenouillet, Yves Morand 2016-08-23
9396984 Method of producing a microelectronic device in a monocrystalline semiconductor substrate with isolation trenches partially formed under an active region Nicolas Loubet, Romain Wacquez 2016-07-19
9379213 Method for forming doped areas under transistor spacers Perrine Batude, Jean-Michel Hartmann, Benoit Sklenard 2016-06-28
9373507 Defective P-N junction for backgated fully depleted silicon on insulator mosfet Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz, Yannick Le Tiec +1 more 2016-06-21
9337350 Transistor with reduced parasitic capacitance and access resistance of the source and drain, and method of fabrication of the same Nicolas Posseme, Laurent Grenouillet, Yannick Le Tiec 2016-05-10
9293474 Dual channel hybrid semiconductor-on-insulator semiconductor devices Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Qing Liu, Laurent Grenouillet +1 more 2016-03-22
9252208 Uniaxially-strained FD-SOI finFET Pierre Morin, Laurent Grenouillet, Ajey Poovannummoottil Jacob 2016-02-02
9252052 Dual shallow trench isolation liner for preventing electrical shorts Bruce B. Doris, Shom Ponoth, Prasanna Khare, Qing Liu, Nicolas Loubet 2016-02-02
9236478 Method for manufacturing a fin MOS transistor Yves Morand, Romain Wacquez, Laurent Grenouillet, Yannick Le Tiec 2016-01-12
9231062 Method for treating the surface of a silicon substrate Yannick Le Tiec, Laurent Grenouillet, Romain Wacquez 2016-01-05
9171757 Dual shallow trench isolation liner for preventing electrical shorts Bruce B. Doris, Shom Ponoth, Prasanna Khare, Qing Liu, Nicolas Loubet 2015-10-27
9136366 Transistor with coupled gate and ground plane Bastien Giraud, Jean-Philippe Noel 2015-09-15
9123814 Field effect device provided with a thinned counter-electrode and method for fabricating Laurent Grenouillet 2015-09-01
9112014 Transistor with counter-electrode connection amalgamated with the source/drain contact Qing Liu 2015-08-18
9105691 Contact isolation scheme for thin buried oxide substrate devices Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz, Yannick Le Tiec +1 more 2015-08-11